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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2001 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS4201 crystalclear ? audio codec ?97 with headphone amplifier features integrated high-performance headphone amplifier on-chip pll for use with external clock sources sample rate converters s/pdif digital audio output ac ?97 2.1 compliant 20-bit stereo digital-to-analog converters 18-bit stereo analog-to-digital converters three analog line-level stereo inputs for line in, video, and aux two analog line-level mono inputs for modem and pc beep dual microphone inputs high quality pseudo-differential cd input integrated high-performance microphone pre-amplifier separate stereo line-level output extensive power management support meets or exceeds the microsoft ? pc 99 and pc 2001 audio performance requirements crystalclear ? 3d stereo enhancement i 2 s serial digital outputs enable cost effective six channel applications description the CS4201 is an ac ? 97 2.1 compliant stereo audio co- dec designed for pc multimedia systems. it uses industry leading crystalclear ? delta-sigma and mixed signal technology. this advanced technology and these features are designed to help enable the design of pc 99 and pc 2001 compliant high-quality audio systems for desktop, portable, and entertainment pcs. coupling the CS4201 with a pci audio accelerator or core logic supporting the ac ? 97 interface, implements a cost effective, superior quality audio solution. the CS4201 surpasses pc 99, pc 2001, and ac ? 97 2.1 au- dio quality standards. ordering info CS4201-jq 48-pin tqfp 9x9x1.4 mm ac?97 registers line cd aux video mic1 mic2 phone pc_beep line_out hp_out mono_out analog input mux and output mixer ac-link and ac ?97 registers pcm_data gain / mute controls input mux output mixer mixer / mux selects ac- link pwr mgt test sync bit_clk sdata_out sdata_in reset# pcm_data src src id0# id1# gpio, s/pdif serial data port gpio0/lrclk gpio1/sdout eapd/sclk spdo/sdo2 18 bit adc 20 bit dac 3d stereo enhancement input mixer apr ? 01 ds483pp3
CS4201 2 ds483pp3 table of contents 1. characteristics and specifications ..................................................................7 analog characteristics ........................................................................................................7 absolute maximum ratings ................................................................................................8 recommended operating conditions.................................................................................8 ac ? 97 serial port timing..................................................................................................10 2. general description ...............................................................................................13 2.1 ac-link .................................................................................................................... ..13 2.2 control registers .......................................................................................................14 2.3 sample rate converters ...........................................................................................14 2.4 mixers ..................................................................................................................... ...14 2.5 input mux .................................................................................................................. .14 2.6 volume control ..........................................................................................................14 3. ac-link frame definition ........................................................................................16 3.1 ac-link serial data output frame ............................................................................17 3.1.1 serial data output slot tags (slot 0) ...........................................................17 3.1.2 command address port (slot 1) ..................................................................17 3.1.3 command data port (slot 2) ........................................................................18 3.1.4 pcm playback data (slots 3-11) .................................................................18 3.1.5 gpio pin control (slot12) ............................................................................18 3.2 ac-link serial data input frame ..............................................................................19 3.2.1 serial data input slot tag bits (slot 0) ......................................................19 3.2.2 status address port (slot 1) .........................................................................19 3.2.3 status data port (slot 2) ..............................................................................20 3.2.4 pcm capture data (slot 3-8) .......................................................................20 3.2.5 gpio pin status (slot 12) ...........................................................................20 3.3 ac-link protocol violation - loss of sync ...............................................................21 4. register interface .............................................................................................22 4.1 reset register (index 00h) ......................................................................................23 4.2 analog mixer output volume registers (index 02h - 04h) ......................................23 4.3 mono volume register (index 06h) ..........................................................................24 4.4 pc_beep volume register (index 0ah) ..................................................................24 4.5 phone volume register (index 0ch) ........................................................................24 4.6 microphone volume register (index 0eh) ................................................................25 4.7 analog mixer input gain registers (index 10h - 18h) ...............................................26 4.8 input mux select register (index 1ah) .....................................................................27 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm microsoft is a registered trademark of microsoft corporation in the united states and/or other countries. intel is a registered trademark of intel corporation. crystalclear is a registered trademark of cirrus logic. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provid ed ? as is ? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or t rade secrets. no part of this publi- cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechan ical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by t he user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any mea ns (electronic, mechanical, photo- graphic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be u sed as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a li st of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
CS4201 ds483pp3 3 4.9 record gain register (index 1ch) ........................................................................... 27 4.10 general purpose register (index 20h) ................................................................. 28 4.11 3d control register (index 22h) ............................................................................. 28 4.12 powerdown control/status register (index 26h) ................................................... 29 4.13 extended audio id register (index 28h) ................................................................ 30 4.14 extended audio status/control register (index 2ah) ............................................ 30 4.15 audio sample rate control registers (index 2ch - 32h) ....................................... 31 4.16 extended modem id register (index 3ch) ............................................................ 32 4.17 extended modem status/control register (index 3eh) ......................................... 32 4.18 gpio pin configuration register (index 4ch) ........................................................32 4.19 gpio pin polarity/type configuration register (index 4eh) .................................. 33 4.20 gpio pin sticky register (index 50h) .................................................................... 33 4.21 gpio pin wakeup mask register (index 52h) ...................................................... 34 4.22 gpio pin status register (index 54h) ................................................................... 34 4.23 ac mode control register (index 5eh) .................................................................. 35 4.24 misc. crystal control register (index 60h) ............................................................. 36 4.25 s/pdif control register (index 68h) ...................................................................... 37 4.26 serial port control register (index 6ah) ................................................................ 38 4.27 vendor id1 register (index 7ch) ........................................................................... 39 4.28 vendor id2 register (index 7eh) ........................................................................... 39 5. serial data ports ..................................................................................................... 40 5.1 overview ................................................................................................................... 40 5.2 multi-channel expansion .......................................................................................... 40 5.3 serial data formats .................................................................................................. 41 6. sony/philips digital interface (s/pdif) ............................................................. 43 7. exclusive functions ................................................................................................ 44 8. power management ................................................................................................. 45 8.1 ac ? 97 reset modes ................................................................................................. 45 8.1.1 cold reset ................................................................................................... 45 8.1.2 warm reset ................................................................................................. 45 8.1.3 new warm reset .........................................................................................45 8.1.4 register reset ............................................................................................. 45 8.2 powerdown controls ................................................................................................. 46 9. clocking .................................................................................................................. ..... 48 9.1 pll operation (external clock) ................................................................................ 48 9.2 24.576 mhz crystal operation ..................................................................................48 9.3 secondary codec operation ..................................................................................... 48 10. analog hardware description ......................................................................... 50 10.1analog inputs ............................................................................................................5 0 10.1.1 line inputs ................................................................................................. 50 10.1.2 cd input ..................................................................................................... 50 10.1.3 microphone inputs ..................................................................................... 51 10.1.4 pc beep input ............................................................................................ 51 10.1.5 phone input ................................................................................................ 51 10.2analog outputs ......................................................................................................... 52 10.2.1 stereo outputs ........................................................................................... 52 10.2.2 mono output .............................................................................................. 52 10.3miscellaneous analog signals ..................................................................................52 10.4power supplies ......................................................................................................... 53 10.5reference design ..................................................................................................... 53 11. grounding and layout ........................................................................................ 54
CS4201 4 ds483pp3 12. pin descriptions ..................................................................................................56 audio i/o pins ............................................................................................................... ..57 analog reference, filter, and configuration pins ...........................................................58 ac-link pins ................................................................................................................. ..59 clock and configuration pins ..........................................................................................60 misc. digital interface pins ..............................................................................................60 power supply pins ..........................................................................................................61 13. parameter and term definitions ......................................................................62 14. reference design .................................................................................................64 15. references ............................................................................................................... .65 16. package dimensions ...............................................................................................66
CS4201 ds483pp3 5 list of figures figure 1. power up timing ...............................................................................................11 figure 2. codec ready from start-up or fault condition ................................................. 11 figure 3. clocks............................................................................................................... .11 figure 4. data setup and hold .........................................................................................12 figure 5. pr4 powerdown and warm reset.................................................................... 12 figure 6. test mode ......................................................................................................... 12 figure 7. ac-link connections .......................................................................................... 13 figure 8. CS4201 mixer diagram ..................................................................................... 15 figure 9. ac-link input and output framing .....................................................................16 figure 10. serial data port: six channel circuit .............................................................. 40 figure 11. serial data format 0 (i2s) .............................................................................. 42 figure 12. serial data format 1 (left justified)................................................................ 42 figure 13. serial data format 2 (right justified, 20-bit data) .......................................... 42 figure 14. serial data format 3 (right justified, 16-bit data) .......................................... 42 figure 15. s/pdif output ................................................................................................. 43 figure 16. pll external loop filter ..................................................................................48 figure 17. external crystal ...............................................................................................48 figure 18. line input (replicate for video and aux) ....................................................... 50 figure 19. differential 2 vrms cd input.......................................................................... 50 figure 20. differential 1 vrms cd input.......................................................................... 50 figure 21. microphone input............................................................................................. 51 figure 22. pc_beep input ...............................................................................................51 figure 23. modem connection .........................................................................................51 figure 24. line out and headphone out setup ...............................................................52 figure 25. line out/headphone out setup ...................................................................... 52 figure 26. +5v analog voltage regulator ........................................................................ 53 figure 27. conceptual layout for the CS4201 when in xtal or osc clocking modes .. 55 figure 28. pin locations for the CS4201.......................................................................... 56 figure 29. CS4201 reference design.............................................................................. 64
CS4201 6 ds483pp3 list of tables table 1. register overview for the CS4201 .....................................................................22 table 2. analog mixer output attenuation ........................................................................23 table 3. microphone input gain values............................................................................25 table 4. analog mixer input gain values .........................................................................26 table 5. analog mixer input gain register index .............................................................26 table 6. input mux selection ............................................................................................27 table 7. record gain values............................................................................................27 table 8. directly supported src sample rates for the CS4201 .....................................31 table 9. gpio input/output configurations ......................................................................33 table 10. slot mapping for the CS4201...........................................................................35 table 11. serial data format selection ............................................................................38 table 12. device id with corresponding part number .....................................................39 table 13. serial data formats and compatible dacs for the CS4201 ...........................41 table 14. powerdown pr bit functions ...........................................................................46 table 15. powerdown pr function matrix for the CS4201 ..............................................47 table 16. power consumption by powerdown mode for the CS4201..............................47 table 17. clocking configurations for the CS4201...........................................................49
CS4201 ds483pp3 7 1. characteristics and specifications analog characteristics (standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v 5%, dvdd = 3.3 v 5%; 1 khz input sine wave; sample frequency, fs = 48 khz; z al =100 k ?/ 1000 pf load for mono and line outputs; c dl = 18 pf load (note 1); measurement bandwidth is 20 hz - 20 khz, 18-bit linear coding for adc functions, 20-bit linear coding for dac functions; mixer registers set for unity gain. notes: 1. z al refers to the analog output pin loading and c dl refers to the digital output pin loading. 2. parameter definitions are given in section 13 , parameter and term definitions . 3. path refers to the signal path used to generate this data. these paths are defined in section 13, parameter and term definitions . 4. this specification is guaranteed by silicon characterization; it is not production tested. parameter (note 2) symbol path (note 3) CS4201-jq unit min typ max full scale input voltage line inputs mic inputs (10db = 0, 20db = 0) mic inputs (10db = 1, 20db = 0) mic inputs (10db = 0, 20db = 1) mic inputs (10db = 1, 20db = 1) a-d a-d a-d a-d a-d 0.91 0.91 0.283 0.091 0.0283 1.00 1.00 0.315 0.10 0.0315 - - - - - v rms v rms v rms v rms v rms full scale output voltage line and mono outputs headphone output d-a d-a 0.91 - 1.0 1.4 1.13 - v rms v rms frequency response (note 4) analog ac = 0.5 db dac ac = 0.5 db adc ac = 0.5 db fr a-a d-a a-d 20 20 20 - - - 20,000 20,000 20,000 hz hz hz dynamic range stereo analog inputs to line_out mono analog input to line_out dac dynamic range adc dynamic range dr a-a a-a d-a a-d 90 85 85 85 95 90 90 90 - - - - db fs a db fs a db fs a db fs a dac snr (-20 db fs input w/ ccir-rms filter on output) snr d-a - 70 - db total harmonic distortion + noise (-3 db fs input signal): line output headphone output dac adc (all inputs) thd+n a-a a-a d-a a-d - - - - -90 -75 -87 -84 -80 -70 -80 -80 db fs db fs db fs db fs power supply rejection ratio (1 khz, 0.5 v rms w/ 5 v dc offset) (note 4) 40 60 - db interchannel isolation 70 87 - db spurious tone (note 4) - -100 - db fs input impedance (note 4) 10 - - k ?
CS4201 8 ds483pp3 analog characteristics (continued) mixer characteristics absolute maximum ratings (avss1 = avss2 = dvss1 = dvss2 = 0 v) recommended operating conditions (avss1 = avss2 = dvss1 = dvss2 = 0 v) parameter (note 2) symbol path (note 3) CS4201-jq unit min typ max external load impedance line output, mono output headphone output 10 32 - - - - k ? ? output impedance line output, mono output headphone output (note 4) - - 730 0.8 - - ? ? input capacitance (note 4) - 5 - pf vrefout 2.3 2.4 2.5 v parameter min typ max unit mixer gain range span pc beep line in, aux, cd, video, mic1, mic2, phone mono out, line out, headphone out adc gain - - - - 45.0 46.5 46.5 22.5 - - - - db db db db step size all volume controls except pc beep pc beep - - 1.5 3.0 - - db db parameter min typ max unit power supplies +3.3 v digital +5 v digital analog -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 v v v total power dissipation (supplies, inputs, outputs) - - 1.25 w input current per pin (except supply pins) -10 - 10 ma output current per pin (except supply pins) -15 - 15 ma analog input voltage -0.3 - avdd+ 0.3 v digital input voltage -0.3 - dvdd + 0.3 v ambient temperature (power applied) -55 - 110 c storage temperature -65 - 150 c parameter symbol min typ max unit power supplies +3.3 v digital +5 v digital analog dvdd1, dvdd2 dvdd1, dvdd2 avdd1, avdd2 3.135 4.75 4.75 3.3 5 5 3.465 5.25 5.25 v v v operating ambient temperature 0 - 70 c
CS4201 ds483pp3 9 digital characteristics (avss = dvss = 0 v) parameter symbol min typ max unit dvdd = 3.3v low level input voltage v il - - 0.80 v high level input voltage v ih 2.15 - - v high level output voltage v oh 3.00 3.25 - v low level output voltage v ol - 0.03 0.35 v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current bit_clk, spdo/sdo2 sdata_in, eapd/sclk gpio0/lrclk, gpio1/sdout (note 4) - - - 24 4 4 - - - ma ma ma dvdd = 5.0 v low level input voltage v il - - 0.80 v high level input voltage v ih 3.25 - - v high level output voltage v oh 4.50 4.95 - v low level output voltage v ol - 0.03 0.35 v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current bit_clk, spdo/sdo2 sdata_in, eapd/sclk gpio0/lrclk, gpio1/sdout (note 4) - - - 24 4 4 - - - ma ma ma
CS4201 10 ds483pp3 ac ? 97 serial port timing standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v, dvdd = 3.3 v; c l = 55 pf load. parameter symbol min typ max unit reset timing reset# active low pulse width t rst_low 1.0 - - s reset# inactive to bit_clk start-up delay (xtl mode) (osc mode) (pll mode) t rst2clk - - - 4.0 4.0 2.5 - - - s s ms 1st sync active to codec ready ? set ? t sync2crd - 62.5 - s vdd stable to reset# inactive t vdd2rst# 100 - - s clocks bit_clk frequency f clk - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter (depends on xtl_in source) - - 750 ps bit_clk high pulse width t clk_high 36 40.7 45 ns bit_clk low pulse width t clk_low 36 40.7 45 ns sync frequency f sync -48-khz sync period t sync_period - 20.8 - s sync high pulse width t sync_high -1.3- s sync low pulse width t sync_low - 19.5 - s data setup and hold output propagation delay from rising edge of bit_clk t co 81012ns input setup time from falling edge of bit_clk t isetup 10 - - ns input hold time from falling edge of bit_clk t ihold 0- -ns input signal rise time t irise 2-6ns input signal fall time t ifall 2-6ns output signal rise time (note 4) t orise 246ns output signal fall time (note 4) t ofall 246ns misc. timing parameters end of slot 2 to bit_clk, sdata_in low (pr4) t s2_pdown - 0.285 1.0 s sync pulse width (pr4) warm reset t sync_pr4 1.0 - - s sync inactive (pr4) to bit_clk start-up delay t sync2clk 162.8 285 - ns setup to trailing edge of reset# (ate test mode) (note 4) t setup2rst 15 - - ns rising edge of reset# to hi-z delay (note 4) t off - - 25 ns
CS4201 ds483pp3 11 bit_clk t rst_low t rst2clk t vdd2rst# vdd reset# figure 1. power up timing figure 2. codec ready from start-up or fault condition bit_clk t sync2crd codec_ready sync figure 3. clocks bit_clk sync t irise t ifall t orise t ifall t clk_high t clk_low t sync_high t sync_low t sync_period t clk_period
CS4201 12 ds483pp3 bit_clk t isetup t ihold t co sdata_out, sync sdata_in figure 4. data setup and hold bit_clk t s2_pdown sdata_in sdata_out sync write to 0x20 data pr4 don ? t care slot 1 slot 2 sync_pr4 sync2clk t t figure 5. pr4 powerdown and warm reset reset# sdata_out, sync t setup2rst sdata_in, t off bit_clk hi-z figure 6. test mode
CS4201 ds483pp3 13 2. general description the CS4201 is a mixed-signal serial audio codec with integrated headphone power amplifier com- pliant with the intel ? audio codec ?97 specifica- tion , revision 2.1 [6] (referred to as ac ? 97). it is designed to be paired with a digital controller, typ- ically located on the pci bus or integrated within the system core logic chip set. the controller is re- sponsible for all communications between the CS4201 and the remainder of the system. the CS4201 contains two distinct functional sections: digital and analog. the digital section includes the ac-link interface, s/pdif interface, serial data port, gpio, power management support, and sam- ple rate converters (srcs). the analog section in- cludes the analog input multiplexer (mux), stereo input mixer, stereo output mixer, mono output mix- er, headphone amplifier, stereo analog-to-digital converters (adcs), stereo digital-to-analog con- verters (dacs), and their associated volume con- trols. 2.1 ac-link all communication with the CS4201 is established with a 5-wire digital interface to the controller called the ac-link. this interface is shown in figure 7. all clocking for the serial communication is synchronous to the bit_clk signal. bit_clk is generated by the primary audio codec and is used to clock the controller and any secondary audio co- decs. both input and output ac-link audio frames are organized as a sequence of 256 serial bits form- ing 13 groups referred to as ? slots ? . during each au- dio frame, data is passed bi-directionally between the CS4201 and the controller. the input frame is driven from the CS4201 on the sdata_in line. the output frame is driven from the controller on the sdata_out line. the controller is also re- sponsible for issuing reset commands via the re- set# signal. following a cold reset, the CS4201 is responsible for notifying the controller that it is ready for operation after synchronizing its internal functions. the CS4201 ac-link signals must use the same digital supply voltage as the controller, ei- ther +5 v or +3.3 v. see section 3, ac-link frame definition , for detailed ac-link information. codec sync bit_clk sdata_out sdata_in reset# digital ac ? 97 controller ac ? 97 figure 7. ac-link connections
CS4201 14 ds483pp3 2.2 control registers the CS4201 contains a set of ac ? 97 compliant control registers, and a set of cirrus logic defined control registers. these registers control the basic functions and features of the CS4201. read access- es of the control registers by the ac ? 97 controller are accomplished with the requested register index in slot 1 of a sdata_out frame. the following sdata_in frame will contain the read data in its slot 2. write operations are similar, with the regis- ter index in slot 1 and the write data in slot 2 of a sdata_out frame. the function of each input and output frame is detailed in section 3, ac-link frame definition . individual register descriptions are found in section 4, register interface . 2.3 sample rate converters the sample rate converters (src) provide high ac- curacy digital filters supporting sample frequencies other than 48 khz to be captured from the CS4201 or played from the controller. ac ? 97 requires sup- port for two audio rates (44.1 and 48 khz). in addi- tion, the intel ? i/o controller hub (ichx) specification [9] requires support for five more au- dio rates (8, 11.025, 16, 22.05, and 32 khz). the CS4201 supports all these rates, as shown in table 8 on page 31. 2.4 mixers the CS4201 input and output mixers are illustrated in figure 8. the stereo input mixer sums together the analog inputs to the CS4201 according to the settings in the volume control registers. the stereo output mixer sums the output of the stereo input mixer with the pc_beep and phone signals. af- ter going through the 3d output mixer, the stereo output mix is then sent to the line_out and hp_out pins of the CS4201. the mono output mixer generates a monophonic sum of the left and right audio channels from the stereo input mixer. the mono output mix is then sent to the mono_out pin on the CS4201. 2.5 input mux the input multiplexer controls which analog input is sent to the adcs. the output of the input mux is converted to stereo 18-bit digital pcm data and transmitted to the controller by means of the ac-link sdata_in signal. 2.6 volume control the CS4201 volume registers control analog input levels to the input mixer and analog output levels, including the master volume level. the pc_beep volume control uses 3 db steps with a range of 0 db to -45 db attenuation. all other analog volume con- trols use 1.5 db steps. the analog inputs have a mixing range of +12 db signal gain to -34.5 db sig- nal attenuation. the analog output volume controls have from 0 db to -46.5 db attenuation for line_out, hp_out, and mono_out.
CS4201 ds483pp3 15 vol mute vol mute vol mute vol vol mute vol vol vol mute boost 1/2 output buffer headphone amplifier output buffer vol vol adc input mux vol adc mute pcm_out pc_beep phone mic1 mic2 line cd video aux analog stereo input mixer analog stereo output mixer master volume headphone volume mono volume mono out select stereo to mono mixer main adc gain main a/d converters mic select mono out line out pcm_in dac main d/a converters 1/2 stereo to mono mixer mute mute mute 3d headphone out 3d output mixer vol mute mute mute pcm out path dac direct mode pc beep bypass figure 8. CS4201 mixer diagram
CS4201 16 ds483pp3 3. ac-link frame definition the ac-link is a bi-directional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. slot 0 is a special reserved time slot containing 16-bits which are used for ac-link protocol infra- structure. slots 1 through 12 contain audio or con- trol/status data. both the serial data output and input frames are defined from the controller per- spective, not from the CS4201 perspective. the controller synchronizes the beginning of a frame with the assertion of the sync signal. figure 9 shows the position of each bit location within the frame. the first bit position in a new se- rial data frame is f0 and the last bit position in the serial data frame is f255. when sync goes active (high) and is sampled active by the CS4201 (on the falling edge of bit_clk), both devices are syn- chronized to a new serial data frame. the data on the sdata_out pin at this clock edge is the final bit of the previous frame ? s serial data. on the next rising edge of bit_clk, the first bit of slot 0 is driven by the controller on the sdata_out pin. on the next falling edge of bit_clk, the CS4201 latches this data in as the first bit of the frame. 20.8 s (48 khz) tag phase data phase 12.288 mhz 81.4 ns sync bit_clk sdata_out sdata_in f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 d19 f255 valid frame slot 1 valid 0 r/w 0 wd15 f36 f57 d19 d18 d19 d19 d18 d19 rd15 0 0 0 0 f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 f255 f36 f57 f255 f255 0 0 gpio int f96 f96 d19 slot 0 slot 1 slot 2 slot 3 slot 4 slots 5-12 slot 2 valid slot 1 valid slot 2 valid codec ready 0 slot 12 valid codec id1 codec id0 slot 12 valid gpio int bit frame position: bit frame position: figure 9. ac-link input and output framing
CS4201 ds483pp3 17 3.1 ac-link serial data output frame in the serial data output frame, data is passed on the sdata_out pin to the CS4201 from the ac ? 97 controller. figure 9 illustrates the serial port timing. the pcm playback data being passed to the CS4201 is shifted out msb first in the most significant bits of each slot. any pcm data from the ac ? 97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions. bits that are reserved should always be ? cleared ? by the ac ? 97 controller. 3.1.1 serial data output slot tags (slot 0) valid frame the valid frame bit determines if any of the following slots contain either valid playback data for the CS4201 or data for read/write operations. when ? set ? , at least one of the other ac-link slots contains valid data. if this bit is ? clear ? , the remainder of the frame is ignored. slot 1 valid the slot 1 valid bit indicates a valid register read/write address for a primary codec. slot 2 valid the slot 2 valid bit indicates valid register write data for a primary codec. slot [3:11] valid the slot [3:11] valid bits indicate the validity of data in their corresponding serial data output slots. if a bit is ? set ? , the corresponding output slot contains valid data. if a bit is ? cleared ? , the corresponding slot will be ignored. slot 12 valid the slot 12 valid bit indicates if output slot 12 contains valid gpio control data. codec id[1:0] the codec id[1:0] bits determine which codec is being accessed during the current ac-link frame. codec id[1:0] = 00 indicates the primary codec is being accessed. codec id[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. a codec id value of 01, 10, or 11 also indicates a valid read/write address and/or valid register write data for a secondary codec. 3.1.2 command address port (slot 1) r/w read/write . when this bit is ? set ? , a read of the ac ? 97 register specified by the register index bits will occur in the ac ? 97 2.x audio codec. when the bit is ? cleared ? , a write will occur. for any read or write access to occur, the valid frame bit (f0) must be ? set ? and the codec id[1:0] bits (f[14:15]) must match the codec id of the ac ? 97 2.x audio codec being accessed. ad- ditionally, for a primary codec, the slot 1 valid bit (f1) must be ? set ? for a read access and both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be ? set ? for a write access. for a secondary codec, both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be ? cleared ? for read and write accesses. see figure 9 for bit frame positions. ri[6:0] register index. the ri[6:0] bits contain the 7-bit register index to the ac ? 97 registers in the CS4201. all registers are defined at word addressable boundaries. the ri0 bit must be ? clear ? to access CS4201 registers. bit 151413121110987654 3 210 valid frame slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid slot 11 valid slot 12 valid res codec id1 codec id0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w ri6 ri5 ri4 ri3 ri2 ri1 ri0 reserved
CS4201 18 ds483pp3 3.1.3 command data port (slot 2) wd[15:0] write data. the wd[15:0] bits contain the 16-bit value to be written to the register. if an ac- cess is a read, this slot is ignored. note: for any write to an ac ? 97 register, the write is defined to be an ? atomic ? access. this means that when the slot 1 valid bit in output slot 0 is ? set ? , the slot 2 valid bit in output slot 0 should always be ? set ? during the same audio frame. no write access may be split across 2 frames. 3.1.4 pcm playback data (slots 3-11) pd[19:0] playback data. the pd[19:0] bits contain the 20-bit pcm (2 ? s complement) playback data for the left and right dacs, serial data ports, and/or the s/pdif transmitter. table 10 on page 35 lists a cross reference for each function and its respective slot. the mapping of a given slot to the dac, serial data port, or s/pdif transmitter is determined by the state of the id[1:0] bits in the extended audio id register (index 28h) and by the sm[1:0] and amap bits in the ac mode control register (index 5eh) . 3.1.5 gpio pin control (slot12) gpio[1:0] gpio pin control. the gpio[1:0] bits control the CS4201 gpio pins configured as outputs. write accesses using gpio pin control bits configured at outputs will be reflected on the gpio pin output on the next ac-link frame. write accesses using gpio pin control bits configured as inputs will have no effect and are ignored. if the gpoc bit in the misc. crystal control reg- ister (index 60h) is ? set ? , the bits in output slot 12 are ignored and gpio pins configured as outputs are controlled through the gpio pin status register (index 54h) . bit 19181716151413121110987654 3210 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 reserved bit 191817161514131211109876543210 pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not implemented gpio1 gpio0 reserved
CS4201 ds483pp3 19 3.2 ac-link serial data input frame in the serial data input frame, data is passed on the sdata_in pin from the CS4201 to the ac ? 97 con- troller. the data format for the input frame is very similar to the output frame. figure 9 on page 16 illus- trates the serial port timing. the pcm capture data from the CS4201 is shifted out msb first in the most significant 18 bits of each slot. the least significant 2 bits in each slot will be ? cleared ? . if the host requests pcm data from the ac ? 97 controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun- cate) to the desired bit depth. bits that are reserved or not implemented in the CS4201 will always be returned ? cleared ? . 3.2.1 serial data input slot tag bits (slot 0) codec ready codec ready. the codec ready bit indicates the readiness of the CS4201 ac-link. immedi- ately after a cold reset this bit will be ? clear ? . once the CS4201 clocks and voltages are sta- ble, this bit will be ? set ? . until the codec ready bit is ? set ? , no ac-link transactions should be attempted by the controller. the codec ready bit does not indicate readiness of the dacs, adcs, vref, or any other analog function. those must be checked in the powerdown con- trol/status register (index 26h) by the controller before any access is made to the mixer reg- isters. any accesses to the CS4201 while codec ready is ? clear ? are ignored. slot 1 valid the slot 1 valid bit indicates slot 1 contains a valid read back address. slot 2 valid the slot 2 valid bit indicates slot 2 contains valid register read data. slot [3:8] valid the slot [3:8] valid bits indicate slot [3:8] contains valid capture data from the CS4201 adcs. if a bit is ? set ? , the corresponding input slot contains valid data. if a bit is ? cleared ? , the corre- sponding slot will be ignored. slot 12 valid the slot 12 valid bit indicates slot 12 contains valid gpio status data. 3.2.2 status address port (slot 1) ri[6:0] register index. the ri[6:0] bits echo the ac ? 97 register address when a register read has been requested in the previous frame. the CS4201 will only echo the register index for a read access. write accesses will not return valid data in slot 1. sr[3:9,11] slot request. if srx is ? set ? , this indicates the CS4201 src does not need a new sample on the next ac-link frame for that particular slot. if srx is ? clear ? , the src indicates a new sample is needed on the following frame. if the vra bit in the extended audio status/control register (index 2ah) is ? clear ? , the sr[3:9,11] bits are always 0. when vra is ? set ? , the src is enabled and the sr[3:9,11] bits are used to request data. bit 1514131211109876543210 codec ready slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid 000 slot 12 valid reserved bit 191817161514131211109876543210 res ri6 ri5 ri4 ri3 ri2 ri1 ri0 sr3 sr4 sr5 sr6 sr7 sr8 sr9 0 sr11 0 reserved
CS4201 20 ds483pp3 3.2.3 status data port (slot 2) rd[15:0] read data. the rd[15:0] bits contain the register data requested by the controller from the previous read request. all read requests will return the read address in the input slot 1 and the register data in the input slot 2 on the following serial data frame. 3.2.4 pcm capture data (slot 3-8) cd[17:0] capture data. the cd [17:0] bits contain 18-bit pcm (2 ? s complement) capture data. the data will only be valid when the respective slot valid bit is ? set ? in input slot 0. the mapping of a given slot to an adc is determined by the state of the id[1:0] bits in the extended audio id register (index 28h) and the sm[1:0] and amap bits in the ac mode control register (index 5eh). the definition of each slot can be found in table 10 on page 35. 3.2.5 gpio pin status (slot 12) gpio[1:0] gpio pin status. the gpio[1:0] bits reflect the status of the CS4201 gpio pins configured as inputs. the pin status of gpio pins configured as outputs will be reflected back on the gpio[1:0] bits of input slot 12 in the next frame. the output gpio pins are controlled by the gpio[1:0] pin control bits in output slot 12. gpio_int gpio interrupt. the gpio_int bit indicates that a gpio interrupt event has occurred. the occurrence of a gpio interrupt is determined by the gpio interrupt requirements as outlined in the gpio pin wakeup mask register (index 52h) description. in this case, the gpio_int bit is cleared by writing a ? 0 ? to the bit in the gpio pin status register (index 54h) correspond- ing to the gpio pin which generated the interrupt. bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 reserved bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 0 0 bit 191817161514131211109876543210 0 0000000000 0 0 0gpio1gpio0reserved gpio _int
CS4201 ds483pp3 21 3.3 ac-link protocol violation - loss of sync the CS4201 is designed to handle sync protocol violations. the following are situations where the sync protocol has been violated: the sync signal is not sampled high for exact- ly 16 bit_clk clock cycles at the start of an audio frame. the sync signal is not sampled high on the 256th bit_clk clock period after the previous sync assertion. the sync signal goes active high before the 256th bit_clk clock period after the previous sync assertion. upon loss of synchronization with the controller, the CS4201 will mute all analog outputs and ? clear ? the codec ready bit in the serial data input frame until two valid frames are detected. during this de- tection period, the CS4201 will ignore all register reads and writes and will discontinue the transmis- sion of pcm capture data.
CS4201 22 ds483pp3 4. register interface reg register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 se4 se3 se2 se1 se0 0 id8 id7 0 0 id4 0 0 0 0 1990h 02h master volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h headphone volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h mono volume mute 0 0 0 0 0 0 0 0 0 mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 0000h 0ch phone volume mute 0 0 0 0 0 0 0 0 0 0 gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute 0 0 0 0 0 0 0 0 20db 0 gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 1ah record select 0 0 0 0 0 sl2 sl1 sl0 0 0 0 0 0 sr2 sr1 sr0 0000h 1ch record gain mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 8000h 20h general purpose pop 0 3d 0 0 0 mix ms lpbk 00 0 0 0 0 0 0000h 22h 3d control 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc 000fh 28h ext ? d audio id id1 id0 0 0 0 0 amap 00 0 0 0 0 0 0vra x201h 2ah ext ? d audio stat/ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vra 0000h 2ch pcm front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm l/r adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 3ch ext ? d modem id id1 id0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x000h 3eh ext ? d modem stat/ctrl 0 0 0 0 0 0 0 pra 0 0 0 0 0 0 0 gpio 0100h 4ch gpio pin config. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gc1 gc0 0003h 4eh gpio pin polarity/type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 gp1 gp0 ffffh 50h gpio pin sticky 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gs1 gs0 0000h 52h gpio pin wakeup mask 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gw1 gw0 0000h 54h gpio pin status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gi1 gi0 0000h cirrus logic defined registers : 5eh ac mode control 0 0 0 0 aspm 0 0 ddm amap spas sm1 sm0 0 0 0 0 0080h 60h misc. crystal control 0 0 0 dpc 0 0 reserved 10db crst reserved gpoc reserved 0 0002h 68h s/pdif control spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro 0000h 6ah serial port control sden 0 0 0 0 0 0 0 0 0 0 0 sdo2 sdsc sdf1 sdf0 0000h 7ch vendor id1 f7f6f5f4f3f2f1f0s7s6s5s4s3s2 s1s0 4352h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 1 rev2 rev1 rev0 5949h table 1. register overview for the CS4201
CS4201 ds483pp3 23 4.1 reset register (index 00h) se[4:0] crystal 3d stereo enhancement. se[4:0] = 00110, indicating this feature is present. id8 18-bit adc resolution. the id8 bit is ? set ? , indicating this feature is present. id7 20-bit dac resolution. the id7 bit is ? set ? , indicating this feature is present. id4 headphone out. the id4 bit is ? set ? , indicating this feature is present. the state of this bit de- pends on the state of the hpcfg pin. default h. the data in this register is read-only data. any write to this register causes a register reset of the audio control (index 00h - 3ah) and cirrus logic defined (index 5ah - 7ah) registers. a read from this register returns configuration information about the CS4201. 4.2 analog mixer output volume registers (index 02h - 04h) mute output mute. setting this bit mutes the line_out_l/r or hp_out_l/r output signals. ml[5:0] output volume left. these bits control the left master output volume. each step corresponds to 1.5 db gain adjustment, with a total available range from 0 db to -46.5 db attenuation. set- ting the ml5 bit sets the left channel attenuation to -46.5 db by forcing ml[4:0] to a ? 1 ? state. ml[5:0] will read back 011111 when ml5 has been ? set ? . see table 2 for further details. mr[5:0] output volume right. these bits control the right master output volume. each step corre- sponds to 1.5 db gain adjustment, with a total available range from 0 db to -46.5 db attenu- ation. setting the mr5 bit sets the right channel attenuation to -46.5 db by forcing mr[4:0] to a ? 1 ? state. mr[5:0] will read back 011111 when mr5 has been ? set ? . see table 2 for further details. default 8000h. this value corresponds to 0 db attenuation and mute ? set ? . if the hpcfg pin is left floating, register 02h controls the master output volume and register 04h controls the head- phone output volume. if the hpcfg pin is tied ? low ? , register 02h controls the headphone volume and register 04h is a read-only register and always returns 0000h when ? read ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0se4se3se2se1se00id8id700id40000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4mr3mr2mr1mr0 mx5..mx0 write mx5..mx0 read gain level 000000 000000 0 db 000001 000001 -1.5 db ?? ... 011111 011111 -46.5 db 100000 0 11111 -46.5 db ... ... ... 111111 011111 -46.5 db table 2. analog mixer output attenuation
CS4201 24 ds483pp3 4.3 mono volume register (index 06h) mute mono mute. setting this bit mutes the mono_out output signal. mm[5:0] mono volume control. the mm[5:0] bits control the mono output volume. each step corre- sponds to 1.5 db gain adjustment, with a total available range from 0 db to -46.5 db attenu- ation. setting the mm5 bit sets the mono attenuation to -46.5 db by forcing mm[4:0] to a ? 1 ? state. mm[5:0] will read back 011111 when mm5 has been ? set ? . see table 2 on page 23 for further attenuation levels. default 8000h. this value corresponds to 0 db attenuation and mute ? set ? . 4.4 pc_beep volume register (index 0ah) mute pc_beep mute. setting this bit mutes the pc_beep input signal. pv[3:0] pc_beep volume control. the pv[3:0] bits control the gain levels of the pc_beep input source to the input mixer. each step corresponds to 3 db gain adjustment, with 0000 = 0 db. the total range is 0 db to -45 db attenuation. default 0000h. this value corresponds to 0 db attenuation and mute ? clear ? . this register has no effect on the pc_beep volume during reset#. 4.5 phone volume register (index 0ch) mute phone mute. setting this bit mutes the phone input signal. gn[5:0] phone volume control. the gn[4:0] bits control the gain level of the phone input source to the input mixer. each step corresponds to 1.5 db gain adjustment, with 01000 = 0 db. the total range is +12 db to -34.5 db attenuation. see table 4 on page 26 for further attenuation levels. default 8008h. this value corresponds to 0 db attenuation and mute ? set ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute000000000mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute0000000000gn4gn3gn2gn1gn0
CS4201 ds483pp3 25 4.6 microphone volume register (index 0eh) mute microphone mute. setting this bit mutes the mic1 or mic2 signal. the selection of the mic1 or mic2 input pin is controlled by the ms bit in the general purpose register (index 20h) . 20db microphone 20 db boost. when ? set ? , the 20db bit enables the +20 db microphone boost block. in combination with the 10db boost bit in the misc. crystal control register (index 60h) this bit allows for variable boost from 0 db to +30 db in steps of 10 db. table 3 summarizes this behavior. gn[4:0] microphone volume control. the gn[4:0] bits are used to control the gain level of the micro- phone input source to the input mixer. each step corresponds to 1.5 db gain adjustment, with 01000 = 0 db. the total range is +12 db to -34.5 db gain. see table 3 for further details. default 8008h. this value corresponds to 0 db gain and mute ? set ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute0000000020db0gn4gn3gn2gn1gn0 gn4 - gn0 gain level 10db = 0, 20db = 0 10db = 1, 20db = 0 10db = 0, 20db = 1 10db = 1, 20db = 1 00000 +12.0 db +22.0 db +32.0 db +42.0 db 00001 +10.5 db +20.5 db +30.5 db +40.5 db ?? ... ... ... 00111 +1.5 db +11.5 db +21.5 db +31.5 db 01000 0.0 db +10.0 db +20.0 db +30.0 db 01001 -1.5 db +8.5 db +18.5 db +28.5 db ?? ... ... ... 11111 -34.5 db -24.5 db -14.5 db -4.5 db table 3. microphone input gain values
CS4201 26 ds483pp3 4.7 analog mixer input gain registers (index 10h - 18h) mute stereo input mute. setting this bit mutes the respective input signal, both right and left inputs. gl[4:0] left volume control. the gl[4:0] bits are used to control the gain level of the left analog input source to the input mixer. each step corresponds to 1.5 db gain adjustment, with 01000 = 0 db. the total range is +12 db to -34.5 db gain. see table 4 for further details. gr[4:0] right volume control. the gr[4:0] bits are used to control the gain level of the right analog input source to the input mixer. each step corresponds to 1.5 db gain adjustment, with 01000 = 0 db. the total range is +12 db to -34.5 db gain. see table 4 for further details. default 8808h. this value corresponds to 0 db gain and mute ? set ? . the analog mixer input gain registers are listed in table 5. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 gx4 - gx0 gain level 00000 +12.0 db 00001 +10.5 db ?? 00111 +1.5 db 01000 0.0 db 01001 -1.5 db ?? 11111 -34.5 db table 4. analog mixer input gain values register index function 10h line in volume 12h cd volume 14h video volume 16h aux volume 18h pcm out volume table 5. analog mixer input gain register index
CS4201 ds483pp3 27 4.8 input mux select register (index 1ah) sl[2:0] left channel source. the sl[2:0] bits select the left channel source to pass to the adcs for recording. see table 6 for possible values. sr[2:0] right channel source. the sr[2:0] bits select the right channel source to pass to the adcs for recording. see table 6 for possible values. default 0000h. this value selects the mic input for both channels. 4.9 record gain register (index 1ch) mute record gain mute. setting this bit mutes the input to the l/r adcs. gl[3:0] left adc gain. the gl[3:0] bits control the input gain on the left channel of the analog source, applied after the input mux and before the adcs. each step corresponds to 1.5 db gain adjustment, with 0000 = 0 db. the total range is 0 db to +22.5 db gain. see table 7 for further details. gr[3:0] right adc gain. the gr[3:0] bits control the input gain on the right channel of the analog source, applied after the input mux and before the adcs. each step corresponds to 1.5 db gain adjustment, with 0000 = 0 db. the total range is 0 db to +22.5 db gain.see table 7 for further details. default 8000h. this value corresponds to 0 db gain and mute ? set ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000sl2sl1sl000000sr2sr1sr0 sx2 - sx0 record source 000 mic 001 cd input 010 video input 011 aux input 100 line input 101 stereo mix 110 mono mix 111 phone input table 6. input mux selection d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 gx4 - gx0 gain level 1111 +22.5 db ?? 0001 +1.5 db 0000 0 db table 7. record gain values
CS4201 28 ds483pp3 4.10 general purpose register (index 20h) pop pcm out path. when ? clear ? , the pcm out path is mixed pre 3d. when ? set ? , the pcm out path is mixed post 3d. 3d 3d enable. when ? set ? , the 3d bit enables the crystalclear ? 3d stereo enhancement. this function is not available in dac direct mode (ddm). mix mono output path. this bit controls the source of the mono output driver. when ? clear ? , the output of the stereo-to-mono mixer is sent to the mono output. when ? set ? , the output of the microphone boost stage is sent to the mono output. the source of the microphone boost stage is controlled by the ms bit in the general purpose register (index 20h) . ms microphone select. the ms bit determines which of the two mic inputs are passed to the mix- er. when ? set ? , the mic2 input is selected. when ? clear ? , the mic1 input is selected. lpbk loopback enable. when ? set ? , the lpbk bit enables the adc/dac loopback mode. this bit routes the output of the adcs to the input of the dacs without involving the ac-link. default 0000h 4.11 3d control register (index 22h) s[3:0] spatial enhancement depth control. the s[3:0] spatial enhancement bits are enabled by the 3d bit in the general purpose register (index 20h) . when s[3:0] = 0000, minimum spatial enhancement is added. when s[3:0] = 1111, maximum spatial enhancement is added. default 0000h. this value corresponds to minimum spatial enhancement. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pop03d000mixmslpbk0000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000s3s2s1s0
CS4201 ds483pp3 29 4.12 powerdown control/status register (index 26h) eapd external amplifier power down. the eapd pin follows this bit and is generally used to power down external amplifiers. the eapd bit is mutually exclusive with the sdsc bit in the serial port control register (index 6ah) . the sdsc bit must be ? clear ? before the eapd bit may be ? set ? . if the sdsc bit is ? set ? , eapd is a read-only bit and always returns ? 0 ? . pr6 headphone amplifier powerdown. when ? set ? , the headphone amplifier is powered down. pr5 internal clock disable. when ? set ? , the internal master clock is disabled (bit_clk running). the only way to recover from setting this bit is through a cold reset (driving the reset# sig- nal active). pr4 ac-link powerdown. when ? set ? , the ac-link is powered down (bit_clk off). the ac-link can be restarted through a warm reset using the sync signal, or a cold reset using the re- set# signal (primary audio codec only). pr3 analog mixer powerdown (vref off). when ? set ? , the analog mixer and voltage reference are powered down. when clearing this bit, the anl, adc, and dac bits should be checked be- fore writing any mixer registers. pr2 analog mixer powerdown (vref on). when ? set ? , the analog mixer is powered down (the volt- age reference is still active). when clearing this bit, the anl bit should be checked before writ- ing any mixer registers. pr1 front dacs powerdown. when ? set ? , the dacs are powered down. when clearing this bit, the dac bit should be checked before sending any data to the dacs. pr0 l/r adcs and input mux powerdown. when ? set ? , the adcs and the adc input muxes are powered down. when clearing this bit, no valid data will be sent down the ac-link until the adc bit goes high. ref voltage reference ready status. when ? set ? , the ref bit indicates the voltage reference is at a nominal level. anl analog ready status. when ? set ? , the analog output mixer, input multiplexer, and volume con- trols are ready. when ? clear ? , no volume control registers should be written. dac front dac ready status. when ? set ? , the dacs are ready to receive data across the ac-link. when ? clear ? , the dacs will not accept any valid data. adc l/r adcs ready status. when ? set ? , the adcs are ready to send data across the ac-link. when ? clear ? , no data will be sent to the controller. default 0000h. this value indicates all blocks are powered on. the lower four bits will change as the CS4201 finishes an initialization and calibration sequence. the pr[6:0] and the eapd bits are powerdown control for different sections of the CS4201 as well as external am- plifiers. the ref, anl, dac, and adc bits are read-only status bits which, when ? set ? , indicate that a particular sec- tion of the CS4201 is ready. after the controller receives the codec ready bit in input slot 0, these status bits must be checked before writing to any mixer registers. see section 8, power management , for more information on the powerdown functions. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc
CS4201 30 ds483pp3 4.13 extended audio id register (index 28h) id[1:0] codec configuration id. these bits indicate the current codec configuration. when id[1:0] = 00, the CS4201 is the primary audio codec. when id[1:0] = 01, 10, or 11, the CS4201 is a secondary audio codec. the state of the id[1:0] bits is determined at power-up from the id[1:0]# pins and the current clocking scheme, see table 17 on page 49. amap audio slot mapping. the amap bit indicates whether the optional ac ? 97 2.1 compliant ac-link slot to audio dac mapping is supported. this bit is a shadow of the amap bit in the ac mode control register (index 5eh) . the pcm playback and capture slots are mapped ac- cording to table 10 on page 35. vra variable rate pcm audio. the vra bit indicates whether variable rate pcm audio is support- ed. this bit always returns ? 1 ? , indicating that variable rate pcm audio is available. default x201h. the extended audio id register (index 28h) is a read-only register. 4.14 extended audio status/control register (index 2ah) vra enable variable rate audio. when ? set ? , the vra bit allows access to the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) . this bit must be ? set ? in order to use variable pcm playback or capture rates. the vra bit also serves as a powerdown for the dac and adc src blocks. clearing vra will reset the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) to their default values. the src data path is flushed and the slot request bits for the currently active dac slots will be fixed at ? 0 ? . default 0000h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1id00000amap00000000vra d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000000vra
CS4201 ds483pp3 31 4.15 audio sample rate control registers (index 2ch - 32h) sr[15:0] sample rate select. the audio sample rate control registers (index 2ch - 32h) control playback and capture sample rates. the pcm front dac rate register (index 2ch) controls the front left and front right dac sample rates. the pcm l/r adc rate register (index 32h) controls the left and right adc sample rates. there are seven sample rates di- rectly supported by this register, shown in table 8. any value written to this register not con- tained intable 8 is not directly supported and will be decoded according to the ranges indicated in the table. the range boundaries have been chosen so that only bits sr[15:12] of each register will have to be considered. all register read transactions will reflect the actual value stored (column 2 in table 8) and not the one attempted to be written. default bb80h. this value corresponds to 48 khz sample rate. writes to the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) are only available in variable rate pcm audio mode when the vra bit in the extended audio status/control register (index 2ah) is ? set ? . if vra = 0, writes to the register are ignored and the register will always read bb80h. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sample rate (hz) sr[15:0], register content (hex value) sr[15:0], decode range (hex value) sr[15:12], decode range (bin value) 8,000 1f40 0000 - 1fff 0000 - 0001 11,025 2b11 2000 - 2fff 0010 - 0010 16,000 3e80 3000 - 3fff 0011 - 0011 22,050 5622 4000 - 5fff 0100 - 0101 32,000 7d00 6000 - 7fff 0110 - 0111 44,100 ac44 8000 - afff 1000 - 1010 48,000 bb80 b000 - ffff 1011 - 1111 table 8. directly supported src sample rates for the CS4201
CS4201 32 ds483pp3 4.16 extended modem id register (index 3ch) id[1:0] codec configuration id. primary is 00; secondary is 01,10,or 11. this is a reflection of the id[1:0]# configuration pins. the state of the id[1:0] bits is determined at power-up from the codec id[1:0]# pins and the current clocking scheme, see table 17 on page 49. default x000h. this value indicates no supported modem functions. the extended modem id register (index 3ch) is a read/write register that identifies the CS4201 modem capabilities. writing any value to this location issues a reset to modem registers (index 3ch-54h) , including gpio registers (index 4ch - 54h) . audio registers are not reset by a write to this location. 4.17 extended modem status/control register (index 3eh) pra gpio powerdown. when ? set ? , the pra bit powers down the gpio subsystem. when the gpio section is powered down, all outputs must be tri-stated and input slot 12 should be marked invalid when the ac-link is active. to use any gpio functionality pra must be cleared first. the serial data mode and the gpio mode of operation are mutually exclusive. to use any gpio function, sden of the serial port control register (index 6ah) must be ? clear ? prior to clearing pra. if the sden bit is ? set ? , pra is a read-only bit and always returns ? 1 ? . gpio gpio. when ? set ? , the gpio bit indicates the gpio subsystem is ready for use. when ? set ? , input slot 12 will also be marked valid. default 0100h 4.18 gpio pin configuration register (index 4ch) gc[1:0] gpio pin configuration. when ? set ? , the gc[1:0] bits define the corresponding gpio pin as an input. when ? clear ? , the corresponding gpio pin is defined as an output. default 0003h. this value corresponds to all gpio pins configured as inputs. after a cold reset or a modem register reset (see extended modem id register (index 3ch) ), all gpio pins are configured as inputs. the upper 14 bits of this register always return ? 0 ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1id000000000000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000pra0000000gpio d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gc1gc0
CS4201 ds483pp3 33 4.19 gpio pin polarity/type configuration register (index 4eh) gp[ 1 :0] gpio pin configuration. this register defines the gpio input polarity (0 = active low, 1 = active high) when a gpio pin is configured as an input. the gp[ 1 :0] bits define the gpio output type (0 = cmos, 1 = open-drain) when a gpio pin is configured as an output. the gc[ 1 :0] bits in the gpio pin configuration register (index 4ch) define the gpio pins as in- puts or outputs. see table 9 for the various gpio configurations. default ffffh after a cold reset or a modem register reset this register defaults to all 1 ? s. the upper 14 bits of this register al- ways return ? 1 ? . 4.20 gpio pin sticky register (index 50h) gs[ 1 :0] gpio pin sticky. this register defines the gpio input type (0 = not sticky, 1 = sticky) when a gpio pin is configured as an input. the gpio pin status of an input configured as ? sticky ? is ? cleared ? by writing a ? 0 ? to the corresponding bit of the gpio pin status register (index 54h) , and by reset. default 0000h after a cold reset or a modem register reset this register defaults to all 0 ? s, specifying ? non-sticky ? . ? sticky ? is de- fined as edge sensitive, ? non-sticky ? as level sensitive. the upper 14 bits of this register always return ? 0 ? . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11111111111111gp1gp0 gcx gpx function configuration 0 0 output cmos drive 0 1 output open drain 1 0 input active low 1 1 input active high (default) table 9. gpio input/output configurations d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gs1gs0
CS4201 34 ds483pp3 4.21 gpio pin wakeup mask register (index 52h) gw[ 1 :0] gpio pin wakeup. this register provides a mask for determining if an input gpio change will generate a wakeup event (0 = no, 1 = yes). when the ac-link is powered up, a wakeup event will be communicated through the assertion of gpio_int = 1 in input slot 12. when the ac-link is powered down ( powerdown control/status register (index 26h) bit pr4 = 1 for pri- mary codecs), a wakeup event will be communicated through a ? 0 ? to ? 1 ? transition on sdata_in. default 0000h gpio bits which have been programmed as inputs, ? sticky ? , and ? wakeup ? , upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause an ac-link wakeup if and only if the ac-link was powered down. once the controller has re-established communication with the CS4201 following a warm reset, it will continue to signal the wakeup event through the gpio_int bit of input slot 12 until the ac ? 97 controller clears the inter- rupt-causing bit in the gpio pin status register (index 54h) ; or the ? wakeup ? , config, or ? sticky ? status of that gpio pin changes. after a cold reset or a modem register reset (see extended modem id register (index 3ch) ) this register defaults to all 0 ? s, specifying no wakeup event. the upper 14 bits of this register always return ? 0 ? . 4.22 gpio pin status register (index 54h) gi[ 1 :0] gpio pin status. this register reflects the state of all gpio pin inputs and outputs. these values are also reflected in slot 12 of every sdata_in frame. gpio inputs configured as ? sticky ? are ? cleared ? by writing a ? 0 ? to the corresponding bit of this register. the gpio_int bit in input slot 12 is ? cleared ? by clearing all interrupt-causing bits in this register. default 0000h gpio pins which have been programmed as inputs and ? sticky ? , upon transition either high-to-low or low-to-high de- pending on pin polarity, will cause the individual gi bit to be ? set ? , and remain ? set ? until ? cleared ? . gpio pins which have been programmed as outputs are controlled either through output slot 12 or through this register, depending on the state of the gpoc bit in the misc. crystal control register (index 60h) . if the gpoc bit is ? cleared ? , the gi bits in this register are read-only and reflect the status of the corresponding gpio output pin ? set ? through output slot 12. if the gpoc bit is ? set ? , the gi bits in this register are read/write bits and control the corresponding gpio output pins. the default value is always the state of the gpio pin. the upper 14 bits of this register should be forced to zero in this register and input slot 12. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gw1gw0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gi1gi0
CS4201 ds483pp3 35 4.23 ac mode control register (index 5eh) aspm analog s/pdif mode. the aspm bit controls the input source to the s/pdif transmitter block. when ? clear ? , the s/pdif transmitter will receive data from the corresponding ac-link output slots. the actual slots are determined by the state of the spas bit. if ? set ? , the s/pdif trans- mitter block will receive data from the adc output. ddm dac direct mode. the ddm bit controls the source of the line output drivers. when this bit is ? clear ? , the CS4201 stereo output mixer drives the line output. when this bit is ? set ? , the CS4201 audio dacs (dac1 and dac2) directly drive the line output. amap audio slot mapping. the amap bit controls whether the CS4201 responds to the codec id based slot mapping as outlined in the ac ? 97 2.1 specification. this bit is shadowed in the extended audio id register (index 28h) . refer to table 10 for the slot mapping configura- tions. spas alternate s/pdif slot mapping. the spas bit controls the mapping of output slots to the s/pdif transmitter. if this bit is ? clear ? (default), the s/pdif transmitter will receive data from the same slots as the dacs. if this bit is ? set ? , alternate (independent) slots will be routed to the s/pdif transmitter. the alternate slots are the same as the sdo2 slots in table 10. sm[1:0] slot map. the sm[1:0] bits define the slot mapping for the CS4201 when the amap bit is ? cleared ? . refer to table 10 for the slot mapping configurations. default 0080h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 aspm 0 0 ddm amap spas sm1 sm0 0000 slot assignment mode codec id slot map amap slot assignments id1 id0 sm1 sm0 dac sdout sdo2 adc spdif for spas = 0 spdif for spas = 1 lrlrlrlr amap mode 000xx 1 34786934 amap mode 101xx 1 34786934 amap mode 210xx 1 7869101178 amap mode 311xx 1 6978101178 slot map mode 0xx00 0 34786934 slot map mode 1xx01 0 7869101178 slot map mode 2xx10 0 6978101178 slot map mode 3xx11 0 511786956 table 10. slot mapping for the CS4201
CS4201 36 ds483pp3 4.24 misc. crystal control register (index 60h) dpc dac phase control. this bit controls the phase of the pcm stream sent to the dacs (after src). when ? cleared ? the phase of the signal will remain unchanged. when this bit is ? set ? , each pcm sample will be inverted before being sent to the dacs. 10db microphone 10 db boost. when ? set ? , the 10db bit enables an additional boost of 10 db on the selected microphone input. in combination with the 20db boost bit in the microphone vol- ume register (index 0eh) this bit allows for variable boost from 0 db to +30 db in steps of 10 db. crst force cold reset. the crst bit is used as an override to the new warm reset behavior defined during pr4 powerdown. if this bit is ? set ? , an active reset# signal will force a cold reset to the CS4201 during a pr4 powerdown. gpoc general purpose output control. the gpoc bit specifies the mechanism by which the status of a general purpose output pin can be controlled. if this bit is ? cleared ? , the gpo status is controlled through the standard ac ? 97 method of setting the appropriate bits in output slot 12. if this bit is ? set ? , the gpo status is controlled through the gpio pin status register (index 54h) . default 0002h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 dpc 0 0 reserved 10db crst reserved gpoc reserved 0
CS4201 ds483pp3 37 4.25 s/pdif control register (index 68h) spen s/pdif enable. the spen bit enables s/pdif data transmission on the spdo/sdo2 pin. the spen bit routes the left and right channel data from the ac ? 97 controller or the adc out- put to the s/pdif transmitter block. the actual data routed to the s/pdif block is controlled through the aspm/amap/sm[1:0]/spas configuration in the ac mode control register (in- dex 5eh) . this bit can only be ? set ? if the sdo2 bit in the serial port control register (index 6ah) is ? 0 ? . if the sdo2 bit is ? set ? , spen is a read-only bit and always returns ? 0 ? . val validity. the val bit is mapped to the v bit (bit 28) of every sub-frame . if this bit is ? clear ? , the signal is suitable for conversion or processing. fs sample rate. the fs bit indicates the sampling rate for the s/pdif data. the inverse of this bit is mapped to bit 25 of the channel status block. when the fs bit is ? clear ? , the sampling frequency is 48 khz. when ? set ? , the sampling frequency is 44.1 khz. the actual rate at which s/pdif data are being transmitted solely depends on the master clock frequency of the CS4201. the fs bit is merely an indicator to the s/pdif receiver. l generation status. the l bit is mapped to bit 15 of the channel status block. for category codes 001xxxx, 0111xxx and 100xxxx, a value of ? 0 ? indicates original material and a value of ? 1 ? indicates a copy of original material. for all other category codes the definition of the l bit is reversed. cc[6:0] category code. the cc[6:0] bits are mapped to bits 8-14 of the channel status block. emph data emphasis. the emph bit is mapped to bit 3 of the channel status block. when ? set ? , 50/15us filter pre-emphasis is indicated. when is ? clear ? , no pre-emphasis is indicated. copy copyright. the copy bit is mapped to bit 2 of the channel status block. if the copy bit is ? set ? copyright is not asserted and copying is permitted. /audio audio / non-audio. the /audio bit is mapped to bit 1 of the channel status block. if the /audio bit is ? clear ? , the data transmitted over s/pdif is assumed to be digital audio. if the /audio bit is ? set ? , non-audio data is assumed. pro professional/consumer. the pro bit is mapped to bit 0 of the channel status block. if the pro bit is ? clear ? , consumer use of the audio control block is indicated. if the bit is ? set ? , professional use is indicated. default 0000h for a further discussion of the proper use of the channel status bits see application note an22: overview of digital audio interface data structures [3] . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro
CS4201 38 ds483pp3 4.26 serial port control register (index 6ah) sden serial data output enable. the sden bit enables transmission of serial data on the sdout pin. the sden bit routes the left and right channel data from the ac ? 97 controller to the serial data port. the actual data routed to the serial data port is controlled through the amap/sm[1:0] configuration in the ac mode control register (index 5eh) . sden also func- tions as a master control for the second serial data output port and the serial clock. this bit can only be ? set ? if the pra bit in the extended modem status and control register (index 3eh) is ? set ? . if the pra bit is ? clear ? , sden is a read-only bit and always returns ? 0 ? . sdo2 serial data output 2 enable. the sdo2 bit enables transmission of serial data on the spdo/sdo2 pin. the sdo2 bit routes the left and right channel data from the ac ? 97 con- troller to the second serial data port. the actual slots routed to the second serial data port are controlled through the amap/sm[1:0] configuration in the ac mode control register (index 5eh) . this bit can only be ? set ? if the sden bit is ? 1 ? and will be ? cleared ? automatically if sden returns to ? 0 ? . furthermore, the sdo2 bit can only be ? set ? if the spen bit in the s/pdif control register (index 68h) is ? 0 ? . if the sden bit is ? 0 ? or the spen bit is ? 1 ? , sdo2 is a read-only bit and always returns ? 0 ? . sdsc serial clock enable. the sdsc bit enables transmission of a serial clock on the eapd/sclk pin. serial data can be routed to dacs that support internal sclk mode without transmitting a serial clock. for dacs that only support external sclk mode, transmission of a serial clock is required and this bit must be set to ? 1 ? . this bit can only be set if the sden bit is ? 1 ? and will be cleared automatically if sden returns to ? 0 ? . furthermore, the sdsc bit can only be ? set ? if the eapd bit in the powerdown control/status register (index 26h) is ? 0 ? . if the sden bit is ? 0 ? or the eapd bit is ? 1 ? , sdsc is a read-only bit and always returns ? 0 ? . sdf[1:0] serial data format. the sdf[1:0] bits control the format of the serial data transmitted on the two output ports. all ports will use the same format. see table 11 for available formats. default 0000h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sden00000000000sdo2sdscsdf1sdf0 sdf1 sdf0 serial data format 00 i 2 s 0 1 left justified 1 0 right justified, 20-bit data 1 1 right justified, 16-bit data table 11. serial data format selection
CS4201 ds483pp3 39 4.27 vendor id1 register (index 7ch) f[7:0] first character of vendor id. with a value of f[7:0] = 43h, these bits define the ascii ? c ? char- acter. s[7:0] second character of vendor id. with a value of s[7:0] = 52h, these bits define the ascii ? r ? character. default 4352h. this register contains read-only data. 4.28 vendor id2 register (index 7eh) t[7:0] third character of vendor id. with a value of t[7:0] = 59h, these bits define the ascii ? y ? character. did[2:0] device id. with a value of did[2:0] = 100, these bits specify the audio codec is a CS4201. rev[2:0] revision. with a value of rev[2:0] = 001, these bits specify the audio codec revision is ? a ? . default 594xh. this register contains read-only data. the two vendor id registers provide a means to determine the manufacturer of the ac ? 97 audio codec. the first three bytes of the vendor id registers contain the ascii code for the first three letters of crystal (cry). the final byte of the vendor id registers is divided into a device id field and a revision field. table 12 lists the currently de- fined device id ? s. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 1 rev2 rev1 rev0 did2-did0 part name 000 cs4297 001 cs4297a 010 cs4294/cs4298 011 cs4299 100 CS4201 101 cs4205 110 cs4291 table 12. device id with corresponding part number
CS4201 40 ds483pp3 5. serial data ports 5.1 overview the CS4201 implements two serial data output ports that can be used for multi-channel expansion. each serial port consists of 4 signals: mclk, sclk, lrclk, and sdata. the existing 256 fs bit_clk will be used as mclk. the clock pins are shared between all the serial ports with only the sdata pins being separate; sdout for the first output port, and sdo2 for the second output port. serial data is transmitted on these ports every ac-link frame. the serial data port is controlled by the sden, sdsc,and sdo2 bits in the serial port control register (index 6ah) . all the serial data port pins are multiplexed with other functions and cannot be used unless the other function is disabled or pow- ered down; see section 7, exclusive functions . some audio dacs can run in an internal sclk mode where sclk is internally derived from mclk and lrclk. in this case, sclk generation in the CS4201 is optional. a feature has been designed into the CS4201 that allows the phase of the internal dacs to be re- versed. this dac phase reversal is controlled by the dpc bit in the misc. crystal control register (index 60h) . this feature is necessary since the phase response for external dacs is unknown and the phase response of the internal dacs can vary depending on the path determined by the pop bit in the general purpose register (index 20h) , the ddm bit in the ac mode control register (index 5eh) , and the output (line_out or hp_out) being used. this feature guarantees that all dacs in a system have the same phase re- sponse, maintaining the accuracy of spatial cues. please note the data sent to the serial ports is straight from the ac-link. there is no src and no volume control available on this data, so it is the re- sponsibility of the controller or host software to provide this functionality if desired. 5.2 multi-channel expansion for multi-channel expansion, the two serial data output ports are used to send ac-link data to one or two external stereo dacs to support up to a total of six channels. the first serial port takes the digital audio data from the sdout slots. the second seri- al port takes the digital audio data from the sdo2 slots. see table 10 on page 35 for the actual slots used depending on configuration. figure 10 shows a six channel application using the CS4201. 8 5 4 3 2 1 4 3 2 18 5 aoutl aoutr sdata dem#/sclk lrck mclk gpio1/sdout spdo/sdo2 44 48 47 43 eapd/sclk gpio0/lrclk line_out_l line_out_r bit_clk 6 36 35 cs4334 aoutl aoutr sdata dem#/sclk lrck mclk cs4334 270k 270k 10uf elec 10uf elec 47k 47k 560 560 2700pf 2700pf left surround right surround 270k 270k 10uf elec 10uf elec 47k 47k 560 560 2700pf 2700pf center lfe agnd agnd agnd agnd left front right front agnd agnd 10uf elec 10uf elec 1000pf agnd 220k 220k agnd 1000pf + + + + + + figure 10. serial data port: six channel circuit
CS4201 ds483pp3 41 5.3 serial data formats in order to support a wide variety of serial audio dacs, the CS4201 can transmit serial data in four different formats. the desired format is selected through the sdf[1:0] bits in the serial port con- trol register (index 6ah) . all serial ports use the same serial data format when enabled. in all cases, lrclk will be synchronous with fs, and sclk will be 64 fs (bit_clk/4). serial data is transi- tioned by the CS4201 on the falling edge of sclk and latched by the dacs on the next rising edge. serial data is shifted out msb first in all supported formats, but lrclk polarity as well as data justi- fication, alignment, and resolution vary. table 13 shows the principal characteristics of each serial format. sdf[1:0] lrclk polarity data justification data alignment (msb vs. lrclk) data resolution timing diagram recommended dac 0 0 negative left justified 1 sclk delayed 20-bit figure 11 cs4334 0 1 positive left justified not delayed 20-bit figure 12 cs4335 1 0 positive right justified not delayed 20-bit figure 13 cs4337 1 1 positive right justified not delayed 16-bit figure 14 cs4338 table 13. serial data formats and compatible dacs for the CS4201
CS4201 42 ds483pp3 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 m s b-1-2-3-4-5 +3 +2 +1 lsb +5 +4 m s b-1-2-3-4 figure 11. serial data format 0 (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 m sb-1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 m sb-1 -2 -3 -4 figure 12. serial data format 1 (left justified) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 19 18 19 18 figure 13. serial data format 2 (right justified, 20-bit data) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 figure 14. serial data format 3 (right justified, 16-bit data)
CS4201 ds483pp3 43 6. sony/philips digital interface (s/pdif) the s/pdif digital output is used to interface the CS4201 to consumer audio equipment external to the pc. this output provides an interface for stor- ing digital audio data or playing digital audio data to digital speakers. figure 15 illustrates the circuits necessary for implementing the iec-958 optical or consumer interface. for further information on s/pdif operation see application note an22: over- view of digital audio interface data structures [3] . for further information on s/pdif recommended transformers see application note an134: aes and s/pdif recommended transformers [4]. 1 2 3 4 5 6 0.1 f r 2 r 1 j1 dgnd dvdd r 1 r 2 spdo/sdo2 s/pdif_out totx-173 spdo/sdo2 +5v_pci dgnd 8.2 k ? dgnd dgnd 3.3v 247.5 ? 107.6 ? 5v 375 ? 93.75 ? t 1 figure 15. s/pdif output
CS4201 44 ds483pp3 7. exclusive functions some of the digital pins on the CS4201 have mul- tiplexed functionality. these functions are mutual- ly exclusive and cannot be requested at the same time. the following pairs of functions are mutually exclusive: gpio and serial data port (gpio0 pin is shared with lrclk pin and gpio1 pin is shared with sdout pin) eapd and serial data port serial clock (eapd pin is shared with sclk pin) s/pdif and second serial data port (spdo pin is shared with sdo2 pin) there is no priority assigned to the exclusive func- tions. a function currently in use must be disabled or powered down before the corresponding exclu- sive function can be enabled. the following control bits for these functions will behave differently than normal bits: the eapd bit in the powerdown con- trol/status register (index 26h) , the pra bit in the extended modem status/control register (index 3eh) , the spen bit in the s/pdif control register (index 68h) , and the sden, sdo2, and sdsc bits in the serial port control register (index 6ah) . these bits can become read-only bits if they control a feature that is currently unavailable because the corresponding exclusive feature is already in use, or the corresponding master control for this feature is not set.
CS4201 ds483pp3 45 8. power management 8.1 ac ?97 reset modes the CS4201 supports four reset methods, as de- fined in the ac ? 97 specification: cold reset , warm reset, new warm reset, and register reset . a cold reset results in all ac ? 97 logic (registers included) initialized to its default state. a warm reset or new warm reset leaves the contents of the ac ? 97 register set unaltered. a register reset initializes only the ac ? 97 registers to their default states. 8.1.1 cold reset a cold reset is achieved by asserting reset# for a minimum of 1 s after the power supply rails have stabilized. this is done in accordance with the minimum timing specifications in the ac ? 97 seri- al port timing section on page 10. once de-assert- ed, all of the CS4201 registers will be reset to their default power-on states and the bit_clk and sdata_in signals will be reactivated. 8.1.2 warm reset a warm reset allows the ac-link to be reactivated without losing information in the CS4201 registers. a warm reset is required to resume from a d3 hot state where the ac-link had been halted yet full power had been maintained. a primary codec warm reset is initiated when the sync signal is driven high for at least 1 s and then driven low in the absence of the bit_clk clock signal. the bit_clk clock will not restart until at least 2 nor- mal bit_clk clock periods (162.8 ns) after the sync signal is de-asserted. a warm reset of the secondary codec is recognized when the primary codec on the ac-link resumes bit_clk genera- tion. the CS4201 will wait for bit_clk to be sta- ble to restore sdata_in activity, s/pdif and/or serial data port transmission on the following frame. 8.1.3 new warm reset the new warm reset also allows the ac-link to be reactivated without losing information in the registers. a new warm reset is required to resume from a d3 cold state where ac-link power has been removed. new warm reset is recognized by the low-high transition of reset# after the ac-link has been programmed into pr4 powerdown. the new warm reset functionality can be disabled by setting the crst bit in the misc. crystal control register (index 60h) . 8.1.4 register reset the last reset mode provides a register reset to the CS4201. this is available only when the CS4201 ac-link is active and the codec ready bit is ? set ? . the audio (including extended audio) control reg- isters (index 00h - 3ah) and the vendor specific registers (index 5ah - 7ah) are reset to their default states by a write of any value to the reset register (index 00h) . the modem (including gpio) regis- ters (index 3ch - 56h) are reset to their default states by a write of any value to the extended mo- dem id register (index 3ch) .
CS4201 46 ds483pp3 8.2 powerdown controls the powerdown control/status register (index 26h) controls the power management func- tions. the pr[6:0] bits in this register control the internal powerdown states of the CS4201. power- down control is available for individual subsections of the CS4201 by asserting any prx bit or any com- bination of prx bits. all powerdown states except pr4 and pr5 can be resumed by clearing the cor- responding prx bit. table 14 shows the mapping of the power control bits to the functions they man- age. when pr0 is ? set ? , the l/r adcs and the input mux are shut down and the adc bit in the power- down control/status register (index 26h) is ? cleared ? indicating the adcs are no longer in a ready state. the same is true for pr1 and the dacs, pr2 and the analog mixer, pr3 and the voltage reference (vrefout), and pr6 and the head- phone amplifier. when one of these bits is ? cleared ? , the corresponding subsystem will begin a power-on process, and the associated status bit will be ? set ? when the hardware is ready. in a primary codec the pr4 bit powers down the ac-link, but all other analog and digital sub- systems continue to function. the required resume sequence from a pr4 state is either a warm reset or a new warm reset, depending on whether a d3 hot or d3 cold state has been entered. the pr5 bit disables all internal clocks and powers down the dacs and the adcs, but maintains oper- ation of the bit_clk and the analog mixer. a cold reset is the only way to restore operation to the CS4201 after asserting pr5. to achieve a com- plete digital powerdown, pr4 and pr5 must be as- serted within a single ac output frame. this will also drive bit_clk ? low ? . the CS4201 does not automatically mute any input or output when the powerdown bits are ? set ? . the software driver controlling the ac ? 97 device must manage muting the input and output analog signals before putting the part into any power management state. the definition of each prx bit may affect a single subsection or a combination of subsections within the CS4201. table 15 contains the matrix of subsections affected by the respective prx func- tion. table 16 shows the different operating power consumptions levels for different powerdown func- tions. pr bit function pr0 l/r adcs and input mux powerdown pr1 front dacs powerdown pr2 analog mixer powerdown (vref on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off)* pr5 internal clock disable pr6 headphone out powerdown * applies only to primary codec table 14. powerdown pr bit functions
CS4201 ds483pp3 47 pr bit adcs dacs mixer analog reference ac link internal clock off headphone pr0 ? pr1 ? pr2 ??? ? pr3 ??? ? ? pr4 ? pr5 ?? ? pr6 ? table 15. powerdown pr function matrix for the CS4201 power state i dvdd (ma) [dvdd=3.3 v] i dvdd (ma) [dvdd=5 v] i avdd1 (ma) i avdd2 (ma) full power + src ? s 27.1 44.3 34.9 5.6 full power + s/pdif 1 1 assuming standard resistive load for transformer coupled coaxial s/pdif output (rload = 292 ohm, dvdd = 3.3 v) (rload = 415 ohm, dvdd = 5 v). general: i dvdd s/pdif = i dvdd + dvdd/rload/2 31.9 48.7 34.9 5.6 full power + hp 2 2 hp_out_l, hp_out_r driving 4 vpp into 32 ohm resistive load. 26.3 42.7 34.9 40.6 full power 26.3 42.7 34.9 5.6 adcs off (pr0) 23.4 38.1 26.0 5.6 dacs off (pr1) 24.5 39.3 28.3 5.6 audio off (pr2) 21.5 34.1 2.9 0.8 a vref off (pr3) 21.2 34.1 2.8 0.8 a hp amp off (pr6) 26.3 42.7 33.1 27 a ac-link off (pr4) 20.9 35.2 34.9 5.6 internal clocks off (pr5) 3.8 6.4 19.8 5.6 digital off (pr4+pr5) 14 a28 a 19.8 5.6 pr3+pr4+pr5 14 a28 a 2.3 0.5 a reset 1.5 a8 a 2.9 0.8 a table 16. power consumption by powerdown mode for the CS4201
CS4201 48 ds483pp3 9. clocking the CS4201 may be operated as a primary or sec- ondary codec. as a primary codec, the system clock for the ac-link may be generated from an ex- ternal 24.576 mhz clock source, a 24.576 mhz crystal, or use the internal phase locked loop (pll). the pll allows the CS4201 to accept exter- nal clock frequencies other than 24.576 mhz. the CS4201 uses the presence or absence of a valid clock on the xtl_in pin in conjunction with the id[1:0]# pins to determine the clocking configura- tion. 9.1 pll operation (external clock) the pll mode is activated if a valid clock is present on xtl_in during the rising edge of reset#. once pll mode is entered, the xtl_out pin is redefined as the pll loop filter, as shown in figure 16. the id[1:0]# inputs deter- mine the configuration of the internal divider ratios required to generate the 12.288 mhz bit_clk output; see table 17 on page 49 for additional de- tails. in pll mode, the CS4201 is configured as a primary codec independent of the state of the id[1:0]# pins. if 24.576 mhz is chosen as the ex- ternal clock input (id[1:0]# inputs both pulled high or left floating), the pll is disabled and the clock is used directly. the loop filter is not required and xtl_out is left unconnected. for all other clock input choices, the loop filter is required. the id[1:0] bits of the extended audio id register (index 28h) and the extended modem id register (index 3ch) will always report 0 in pll mode. 9.2 24.576 mhz crystal operation if a valid clock is not present on xtl_in during the rising edge of reset#, the device disables the pll input and latches the state of the id[1:0]# in- puts. if the id[1:0]# inputs are both pulled high or left floating, the device is configured as a primary codec. an external 24.576 mhz crystal is used as the system clock as shown in figure 17. 9.3 secondary codec operation if a valid clock is not present on xtl_in and either id[1:0]# input is pulled low during the rising edge of reset#, the device is determined to be a sec- ondary codec. the bit_clk pin is configured as an input and the CS4201 is driven from the 12.288 mhz bit_clk of the primary codec. the id[1:0] bits of the extended audio id register (index 28h) and the extended modem id register (index 3ch) will report the state of the id[1:0]# inputs. figure 16. pll external loop filter xtl_out xtl_in 2.2 k ? 0.022 uf 220 pf clock source dgnd 22 pf 22 pf 24.576 mhz dgnd xtl_out xtl_in figure 17. external crystal
CS4201 ds483pp3 49 external clock on xtl_in id1# id0# ac-link timing mode codec id clock source clock rate (mhz) pll active application notes yes 1 1 primary 0 external 24.576 no clock generator driving xtl_in yes 1 0 primary 0 external 14.31818 yes external clock source driving xtl_in loop filter connected to xtl_out yes 0 1 primary 0 external 27.000 yes yes 0 0 primary 0 external 48.000 yes no 1 1 primary 0 xtal 24.576 no crystal connected to xtl_in, xtl_out no 1 0 secondary 1 bit_clk 12.288 no bit_clk from primary codec driving bit_clk on all secondary codecs no 0 1 secondary 2 bit_clk 12.288 no no 0 0 secondary 3 bit_clk 12.288 no table 17. clocking configurations for the CS4201
CS4201 50 ds483pp3 10. analog hardware description the analog input section consists of four stereo line-level inputs (line_l/r, cd_l/gnd/r, video_l/r, and aux_l/r), two selectable mono microphone inputs (mic1 and mic2), and two mono inputs (pc_beep and phone). the an- alog output section consists of a mono output (mono_out), a stereo headphone output (hp_out_l/r), and a stereo line-level output (line_out_l/r). this section describes the ana- log hardware needed to interface with these pins. the designs presented in this section are compliant with chapter 17 of microsoft ? s ? pc 99 system de- sign guide [7] (referred to as pc 99) and chapter 11 of microsoft ? s ? pc 2001 system design guide [8] (referred to as pc 2001). for information on emi reduction techniques refer to the application note an165: cs4297a/cs4299 emi reduction techniques [5]. 10.1 analog inputs all analog inputs to the CS4201, including cd_gnd, should be capacitively coupled to the input pins. unused analog inputs should be tied to- gether and connected through a capacitor to analog ground or tied to the vrefout pin directly. the max- imum allowed voltage for analog inputs, except the microphone input, is 1 v rms . the maximum al- lowed voltage for the microphone input depends on the selected boost setting. 10.1.1 line inputs figure 18 shows circuitry for a line-level stereo in- put. replicate this circuit for the line, video and aux inputs. this design attenuates the input by 6 db, bringing the signal from the pc 99 specified 2v rms , to the CS4201 maximum allowed 1 v rms . 10.1.2 cd input the cd line-level input has an extra pin, cd_gnd, providing a pseudo-differential input for both cd_l and cd_r. this pin takes the common-mode noise out of the cd inputs when connected to the cd analog source ground. follow- ing the reference designs in figure 19 and figure 20 provides extra attenuation of common mode noise coming from the cd-rom drive, thereby producing a higher quality signal. one per- cent resistors are recommended since closely matched resistor values provide better com- mon-mode attenuation of unwanted signals. the circuit shown in figure 19 can be used to attenuate a 2 v rms cd input signal by 6 db. the circuit shown in figure 20 can be used for a 1 v rms cd in- put signal. line_in_r line_in_l 6.8 k ? 1.0 f 1.0 f agnd agnd 6.8 k ? 6.8 k ? 6.8 k ? figure 18. line input (replicate for video and aux) (all resistors 1%) 6.8 k ? cd_l cd_com cd_r 1.0 f cd_l cd_r cd_gnd 6.8 k ? 1.0 f 3.4 k ? 6.8 k ? 2.2 f 3.4 k ? 6.8 k ? agnd figure 19. differential 2 v rms cd input 100 ? cd_l cd_com cd_r 1.0 f cd_l cd_r cd_gnd 100 ? 1.0 f 100 ? 47 k ? 2.2 f 47 k ? 47 k ? agnd figure 20. differential 1 v rms cd input
CS4201 ds483pp3 51 10.1.3 microphone inputs figure 21 illustrates an input circuit suitable for dy- namic and electret microphones. electret, also known as phantom-powered, microphones use the right channel (ring) of the jack for power. the de- sign also supports the recommended advanced fre- quency response for voice recognition as specified in pc 99 and pc 2001. the microphone input of the CS4201 has an integrated pre-amplifier. using combinations of the 10db bit in the misc. crystal control register (index 60) and the 20db bit in the mic volume register (index 0eh) the pre-amplifier gain can be set to 0 db, 10 db, 20 db, or 30 db. 10.1.4 pc beep input the pc_beep input is useful for mixing the output of the ? beeper ? (timer chip), provided in most pcs, with the other audio signals. when the CS4201 is held in reset, pc_beep is passed directly to the line output. this allows the system sounds or ? beeps ? to be available before the ac ? 97 interface has been activated. figure 22 illustrates a typical input circuit for the pc_beep input. if pc_beep is driven from a cmos gate, the 4.7 k ? resistor should be tied to analog ground instead of +5va. although this input is described for a low-quality ? beeper ? , it is of the same high-quality as all other analog inputs and may be used for other purposes. 10.1.5 phone input one application of the phone input is to interface to the output of a modem analog front end (afe) device so that modem dialing signals and protocol negotiations may be monitored through the audio system. figure 23 shows a design for a modem connection where the output is fed from the CS4201 mono_out pin through a divider. the divider ratio shown does not attenuate the signal, providing an output voltage of 1 v rms . if a lower output voltage is desired, the resistors can be re- placed with appropriate values, as long as the total load on the output is kept greater than 10 k ? . the phone input is divided by 6 db to accommodate a line-level source of 2 v rms . 0.1 f x7r 100 ? 0.1 f x7r mic1/mic2 10 f elec agnd +5va 2.2 k ? 1.5 k ? agnd agnd + figure 21. microphone input 4.7 k ? pc_beep +5va (low noise) or agnd if cmos source pc-beep-bus 47 k ? 2.7 nf x7r 0.1 f x7r agnd figure 22. pc_beep input phone mono_out phone mono_out 6.8 k ? 1.0 f 0 ? 6.8 k ? 1.0 f 47 k ? agnd agnd 1000 pf figure 23. modem connection
CS4201 52 ds483pp3 10.2 analog outputs the analog output section provides a stereo, a headphone, and a mono output. the mono_out, line_out_l, and line_out_r pins require 680 pf to 1000 pf npo dielectric capacitors be- tween the corresponding pin and analog ground. each analog output is dc-biased up to the vrefout voltage signal reference, nominally 2.4 v. this re- quires the outputs be ac-coupled to external cir- cuitry (ac loads must be greater than 10 k ? for the line output or 32 ? for the headphone output). the headphone coupling capacitors should be 220 f or greater to minimize low frequency roll-off. 10.2.1 stereo outputs the line_out and hp_out stereo outputs de- pend on the configuration of the hpcfg pin. as shown in figure 24, if the hpcfg pin is left float- ing, the part behaves as specified in ac ? 97. as shown in figure 25, if the hpcfg pin is grounded, the part behaves as if hp_out was the only out- put. in this case, line_out will be muted, the master volume register (index 02h) will control hp_out and pc_beep will be routed to hp_out during reset. 10.2.2 mono output the mono output, mono_out, can be either a sum of the left and right output channels, attenuat- ed by 6 db to prevent clipping at full scale, or the selected mic signal. the mono out channel can drive the pc internal mono speaker using an appro- priate buffer circuit 10.3 miscellaneous analog signals the aflt1 and aflt2 pins must have a 1000 pf npo capacitor to analog ground. these capacitors provide a single-pole low-pass filter at the inputs to the adcs. this makes low-pass filters at each ana- log input pin unnecessary. the refflt pin must have a short, wide trace to a 2.2 f and a 0.1 f capacitor connected to analog ground (see figure 27 in section 11, grounding and layout , for an example). the 2.2 f capacitor must not be replaced by any other value and must be ceramic with low leakage current. electrolytic capacitors should not be used. no other connection should be made, as any coupling onto this pin will degrade the analog performance of the CS4201. likewise, digital signals should be kept away from refflt for similar reasons. hp_out_r hp_out_c hp_out_l 220 f elec 220 f elec 1 f elec 10 k ? 10 k ? agnd agnd line_out_r line_out_l 10 f elec 10 f elec 220 k ? 220 k ? agnd agnd headphone jack line out jack hpcfg 1000 pf 1000 pf agnd + + + + + figure 24. line out and headphone out setup hp_out_r hp_out_c hp_out_l 220 f elec 220 f elec 1 f elec 10 k ? 10 k ? agnd agnd line_out_r line_out_l line out/ headphone jack hpcfg agnd + + + figure 25. line out/headphone out setup
CS4201 ds483pp3 53 10.4 power supplies the power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog per- formance. one analog power pin, avdd2, supplies power to the headphone amplifier on the CS4201. the other analog power pin, avdd1, supplies pow- er to the rest of the CS4201 analog circuitry. the +5 v analog supply should be generated from a voltage regulator (7805 type) connected to a +12 v supply. this helps isolate the analog circuitry from noise typically found on +5 v digital supplies. a typical voltage regulator circuit for analog power using a mc78m05cdt +5v regulator is shown in figure 26. the digital power pins, dvdd1 and dvdd2, should be connected to the same digital supply as the controller ? s ac-link interface. since the digital interface on the CS4201 may operate at either +3.3 v or +5 v, proper connection of these pins will depend on the digital power supply of the controller. 10.5 reference design see section 14 for a CS4201 reference design. figure 26. +5v analog voltage regulator 3 2 1 agnd gnd in out mc78m05cdt +12vd 10 f elec + 0.1 f y5v 10 f elec + 0.1 f y5v dgnd +5va
CS4201 54 ds483pp3 11. grounding and layout figure 27 shows the conceptual layout for the CS4201 in xtal or osc clocking modes. the de- coupling capacitors should be located physically as close to the pins as possible. also, note the connec- tion of the refflt decoupling capacitors to the ground return trace connected directly to the ground return pin, avss1. it is strongly recommended that separate analog and digital ground planes be used. separate ground planes keep digital noise and return currents from modulating the CS4201 ground potential and de- grading performance. the digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections of the CS4201 and any other external analog cir- cuitry. all analog components and traces should be located over the analog ground plane and all digital components and traces should be located over the digital ground plane. the common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located under the CS4201. the ac-link digital interface connec- tion traces should be routed such that the digital ground plane lies underneath these signals (on the internal ground layer). this applies along the entire length of these traces from the ac ? 97 controller to the CS4201. refer to the application note an18: layout and design rules for data converters and other mixed signal devices [2] for more information on layout and design rules.
CS4201 ds483pp3 55 analog ground pin 1 0.1 f 1000 pf npo 2.2f 0.1 f y5v 0.1 f y5v y5v 0.1 f y5v avdd2 av aflt2 refflt avss1 avdd1 aflt1 via to +5vd or +3.3vd via to +5vd or +3.3vd via to digital ground dvss2 dvss1 dvdd1 dvdd2 via to analog ground via to analog ground via to +5va vrefout tovia via to +5va ss2 digital ground figure 27. conceptual layout for the CS4201 when in xtal or osc clocking modes
CS4201 56 ds483pp3 12. pin descriptions CS4201 48 47 46 45 44 43 42 41 40 39 38 37 mono_out avdd2 hp_out_l hp_out_c hp_out_r avss2 gpio0/lrclk gpio1/sdout id0# id1# eapd/sclk spdo/sdo2 1 2 3 4 5 6 7 8 9 10 11 12 dvdd1 xtl_in xtl_out dvss1 sdata_out bit_clk dvss2 sdata_in dvdd2 sync reset# pc_beep 13 14 15 16 17 18 19 20 21 22 23 24 line_in_r line_in_l mic2 mic1 cd_r cd_gnd cd_l video_r video_l aux_r aux_l phone 36 35 34 33 32 31 30 29 28 27 26 25 line_out_r line_out_l flto flti flt3d hpcfg aflt2 aflt1 vrefout refflt avss1 avdd1 figure 28. pin locations for the CS4201
CS4201 ds483pp3 57 audio i/o pins pc_beep - analog mono source, input, pin 12 the pc_beep input is intended to allow the pc system post (power on self-test) tones to pass through to the audio subsystem. the pc_beep input has two connections: the first connection is to the analog output mixer, the second connection is directly to the line_out stereo outputs (if hpcfg is floating) or through the headphone amplifier to the hp_out pins (if hpcfg is tied low). while the reset# pin is actively being asserted to the CS4201, the pc_beep bypass path to the line_out outputs is enabled. while the CS4201 is in normal operation mode with reset# de-asserted, pc_beep is a monophonic source to the analog output mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. phone - analog mono source, input, pin 13 this analog input is a monophonic source to the output mixer. it is intended to be used as a modem subsystem input to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic1 - analog mono source, input, pin 21 this analog input is a monophonic source to the analog output mixer. it is intended to be used as a desktop microphone connection to the audio subsystem. the CS4201 internal mixer ? s microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic2 - analog mono source, input, pin 22 this analog input is a monophonic source to the analog output mixer. it is intended to be used as an alternate microphone connection to the audio subsystem. the CS4201 internal mixer ? s microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. line_in_l, line_in_r - analog line source, inputs, pins 23 and 24 these inputs form a stereo input pair to the CS4201. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or ac-coupled to analog ground. cd_l, cd_r - analog cd source, inputs, pins 18 and 20 these inputs form a stereo input pair to the CS4201. it is intended to be used for the red book cd audio connection to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or ac-coupled to analog ground. cd_gnd - analog cd common source, input, pin 19
CS4201 58 ds483pp3 this analog input is used to remove common mode noise from red book cd audio signals. the impedance on the input signal path should be one half the impedance on the cd_l and cd_r input paths. this pin requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground.
CS4201 ds483pp3 59 video_l, video_r - analog video audio source, inputs, pins 16 and 17 these inputs form a stereo input pair to the CS4201. it is intended to be used for the audio signal output of a video device. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or ac-coupled to analog ground. aux_l, aux_r - analog auxiliary source, inputs, pins 14 and 15 these inputs form a stereo input pair to the CS4201. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or ac-coupled to analog ground. line_out_l, line_out_r - analog line-level, outputs, pins 35 and 36 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 1 v rms (sinusoidal). these outputs are internally biased at the vrefout voltage reference and require either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage. these pins need a 680-1000 pf npo capacitor attached to analog ground. hp_out_l, hp_out_r - analog headphone, outputs, pins 39 and 41 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 4 v pp . these outputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. the hp_out pins can directly drive resistive loads as low as 32 ? (such as standard consumer headphones). capacitive loading must not exceed 200 pf per pin. the outputs are short circuit protected for infinite duration. hp_out_c - analog headphone output common source, input, pin 40 this analog input is used to remove common mode noise from the headphone outputs. this is achieved by biasing the headphone amplifier with the common mode noise on the headphone amplifier ground plane. this pin should be ac-coupled through a 1 f electrolytic capacitor to analog ground (avss2) near the headphone jack. mono_out - analog mono line-level, output, pin 37 this signal is an analog output from the stereo-to-mono mixer. the full-scale output voltage for this output is nominally 1 v rms (sinusoidal). this output is internally biased at the vrefout voltage reference and requires either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage. this pin needs a 680-1000 pf npo capacitor attached to analog ground. analog reference, filter, and configuration pins refflt - internal reference voltage, input, pin 27 this signal is the voltage reference used internal to the CS4201. a 0.1 f and a 2.2 f ceramic capacitor with short, wide traces must be connected to this pin. no other connections should be made to this pin. do not use an electrolytic 2.2 f capacitor, use a type z5u or y5v ceramic capacitor. vrefout - voltage reference, output, pin 28 all analog inputs and outputs are centered around vrefout, nominally 2.4 volts. this pin may be used to bias external amplifiers. it can also drive up to 5 ma of dc which can be used for microphone bias.
CS4201 60 ds483pp3 aflt1 - left adc channel antialiasing filter, input, pin 29 this pin needs a 1000 pf npo capacitor connected to analog ground. aflt2 - right adc channel antialiasing filter, input, pin 30 this pin needs a 1000 pf npo capacitor connected to analog ground. flti, flto - filter input/filter output, pins 33 and 34 a 1000 pf capacitor must be attached between flti and flto if the 3d function is used. flt3d - 3d filter, pin 32 a 0.01 f x7r capacitor must be attached from this pin to agnd if the 3d function is used. hpcfg - headphone configuration, input, pin 31 this pin is the configuration control for the signal routing to the headphone amplifier. if this pin is left floating, the line_out and hp_out pins function as defined in the ac ? 97 specification. if the hpcfg pin is grounded, the hp_out pins behave as a buffered line output. in addition, the line_out pins are muted, the control register for the headphone output will be the master output volume register (index 02h) , and pc_beep is routed to the hp_out pins during reset. the hpcfg pin is internally pulled up to the analog supply voltage. ac-link pins reset# - ac ? 97 chip reset, input, pin 11 this active low signal is the asynchronous cold reset input to the CS4201. the CS4201 must be reset before it can enter normal operating mode. sync - ac-link serial port sync pulse, input, pin 10 sync is the serial port timing signal for the ac-link. its period is the reciprocal of the maximum sample rate, 48 khz. the signal is generated by the controller and is synchronous to bit_clk. sync is an asynchronous input when the CS4201 is configured as a primary codec and is in a pr4 powerdown state. a series terminating resistor of 47 ? should be connected on this signal close to the controller. bit_clk - ac-link serial port master clock, input/output, pin 6 this input/output signal controls the master clock timing for the ac-link. in primary mode, this signal is a 12.288 mhz output clock derived from either a 24.576 mhz crystal or from the internal pll based on the xtl_in input clock. when the CS4201 is in secondary mode, this signal is an input which controls the ac-link serial interface and generates all internal clocking including the ac-link serial interface timing and the analog sampling clocks. a series terminating resistor of 47 ? should be connected on this signal close to the CS4201 in primary mode or close to the bit_clk source in secondary mode. sdata_out - ac-link serial data input stream to ac ? 97, input, pin 5 this input signal receives the control information and digital audio output streams. the data is clocked into the CS4201 on the falling edge of bit_clk. a series terminating resistor of 47 ? should be connected on this signal close to the controller. sdata_in - ac-link serial data output stream from ac ? 97, output, pin 8 this output signal transmits the status information and digital audio input streams from the adcs. the data is clocked out of the CS4201 on the rising edge of bit_clk. a series terminating resistor of 47 ? should be connected on this signal close to the CS4201.
CS4201 ds483pp3 61 clock and configuration pins xtl_in - crystal input/clock input, pin 2 this pin requires either a 24.576 mhz crystal, with the other pin attached to xtl_out, or an external cmos clock. xtl_in must have a crystal or clock source attached for proper operation except when operating in secondary codec mode. the crystal frequency must be 24.576 mhz and designed for fundamental mode, parallel resonance operation. if an external cmos clock is used to drive this pin, it must run at one of these acceptable frequencies: 14.31818. 24.576, 27, or 48 mhz. when configured as a secondary codec, all timing is derived from the bit_clk input signal and this pin should be left floating. see section 9, clocking , for additional details. xtl_out - crystal output/ pll loop filter, pin 3 this pin is used for a crystal placed between this pin and xlt_in. if an external 24.576 mhz clock is used on xtl_in, this pin must be left floating with no traces or components connected to it. if one of the other acceptable clocks is used on xtl_in, this pin must be connected to a loop filter circuit. see section 9, clocking , for additional details. id1#, id0# - codec id, inputs, pins 45 and 46 these pins select the codec id for the CS4201, as well as determine the rate of the incoming clock in pll mode. they are only sampled after the rising edge of reset#. these pins are internally pulled up to the digital supply voltage and should be left floating for logic ? 0 ? or tied to digital ground for logic ? 1 ? . misc. digital interface pins spdo/sdo2 - sony/philips digital interface / serial data output 2,output, pin 48 this pin generates the s/pdif digital output from the CS4201 when the spen bit in the s/pdif control register (index 68h) is ? set ? . this output may be used to directly drive a resistive divider and coupling transformer to an rca-type connector for use with consumer audio equipment. this pin also provides the serial data for the second serial data port when the sdo2 bit in the serial port control register (index 6ah) is ? set ? . these two functions are mutually exclusive. when neither function is being used this output is driven to a logic ? 0 ? . eapd/sclk - external amplifier powerdown / serial clock, output, pin 47 this pin is used to control the powerdown state of an audio amplifier external to the CS4201. the output is controlled by the eapd bit in the powerdown ctrl/stat register (index 26h). it is driven as a normal cmos output and defaults low ( ? 0 ? ) upon power-up. this pin also provides the serial clock for both serial data ports when the sdsc bit in the serial port control register (index 6ah) is ? set ? . gpio0/lrclk - general purpose i/o / left-right clock, input/output, pin 43 this pin is a general purpose i/o pin that can be used to interface with various external circuitry. when configured as an input, it functions as a schmitt triggered input with 350 mv hysteresis at 5 v and 220 mv hysteresis at 3.3 v. when configured as an output, it can function as a normal cmos output (4 ma drive) or as an open drain output. this pin also provides the l/r clock for both serial data ports when the sden bit in the serial port control register (index 6ah) is ? set ? . this bit powers up in the high impedance state for backward compatibility.
CS4201 62 ds483pp3 gpio1/sdout - general purpose i/o / serial data ouput, input/output, pin 44 this pin is a general purpose i/o pin that can be used to interface with various external circuitry. when configured as an input, it functions as a schmitt triggered input with 350 mv hysteresis at 5 v and 220 mv hysteresis at 3.3 v. when configured as an output, it can function as a normal cmos output (4 ma drive) or as an open drain output. this pin also provides the serial data for the first serial data port when the sden bit in the serial port control register (index 6ah) is ? set ? . this bit powers up in the high impedance state for backward compatibility. power supply pins dvdd1, dvdd2 - digital supply voltage, pins 1 and 9 digital supply voltage for the ac-link section of the CS4201. these pins can be tied to +5 v digital or to +3.3 v digital. the CS4201 and controller ? s ac-link should share a common digital supply. dvss1, dvss2 - digital ground, pins 4 and 7 digital ground connection for the ac-link section of the CS4201. these pins should be isolated from analog ground currents. avdd1, avdd2 - analog supply voltage, pins 25 and 38 analog supply voltage for the analog and mixed signal section of the CS4201 (avdd1) as well as the headphone amplifier (avdd2). these pins must be tied to the analog +5 v power supply. it is strongly recommended that +5 v be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. avss1, avss2 - analog ground, pins 26 and 42 ground connection for the analog, mixed signal, and substrate sections of the CS4201 (avss1) as well as the headphone amplifier (avss2). these pins should be isolated from digital ground currents.
CS4201 ds483pp3 63 13. parameter and term definitions ac ? 97 specification refers to the audio codec ?97 component specification ver 2.1 published by the intel ? corporation [6]. ac ? 97 controller or controller refers to the control chip which interfaces to the audio codec ac-link. this has been also called dc ? 97 for digital controller ? 97 [6]. ac ? 97 registers or codec registers refers to the 64-field register map defined in the ac ? 97 specification. adc refers to a single analog-to-digital converter in the CS4201. ? adcs ? refers to the stereo pair of analog-to-digital converters. the CS4201 adcs have 18-bit resolution. codec refers to the chip containing the adcs, dacs, and analog mixer. in this data sheet, the codec is the CS4201. dac refers to a single digital-to-analog converter in the CS4201. ? dacs ? refers to the stereo pair of digital-to-analog converters. the CS4201 dacs have 20-bit resolution. db fs a db fs is defined as db relative to full-scale. the ? a ? indicates an a weighting filter was used. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. dynamic range (dr) dr is the ratio of the rms full-scale signal level divided by the rms sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a. fft fast fourier transform. frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. fs sampling frequency. interchannel gain mismatch for the adcs, the difference in input voltage to get an equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units are in db.
CS4201 64 ds483pp3 interchannel isolation the amount of 1 khz signal present on the output of the grounded ac-coupled line input channel with 1 khz, 0 db, signal present on the other line input channel. units are in db. line-level refers to a consumer equipment compatible, voltage driven interface. the term implies a low driver impedance and a minimum 10 k ? load impedance. paths a-d: analog in, through the adcs, onto the serial link. d-a: serial interface inputs through the dacs to the analog output. a-a: analog in to analog out (analog mixer). pc 99 refers to the pc 99 system design guide published by the microsoft ? corporation [7]. pc 2001 refers to the pc 2001 system design guide published by the microsoft ? corporation [8]. pll phase lock loop. circuitry for generating a desired clock from an external clock source. resolution the number of bits in the output words to the dacs, and in the input words to the adcs. signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinusoidal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. s/pdif sony/phillips digital interface. this interface was established as a means of digitally interconnecting consumer audio equipment. the documentation for s/pdif has been superseded by the iec-958 consumer digital interface document. src sample rate converter. converts data derived at one sample rate to a differing sample rate. the CS4201 operates at a fixed sample frequency of 48 khz. the internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 khz. total harmonic distortion plus noise (thd+n) thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. it is tested using a -3 db fs input signal and is measured over a 20 hz to 20 khz bandwidth with units in db fs.
CS4201 ds483pp3 65 14. reference design r17 6.8k c17 220uf elec + r11 10k r5 6.8k c33 22pf npo c7 10uf elec + c12 10uf elec + c1 0.1uf x7r r6 6.8k c32 22pf npo j1 2x1hdr-sn/pb 1 2 r3 6.8k c9 0.1uf x7r c20 10uf elec + c23 1000pf npo j2 4x1hdr-au 1 2 3 4 c25 0.01uf x7r r7 47 c22 0.1uf x7r c15 220uf elec + j7 phono-1/8 4 3 5 2 1 c2 2700pf x7r y1 24.576 mhz r1 47k c30 10uf elec + r16 6.8k r15 6.8k c11 0.1uf x7r r4 6.8k r19 2.2k j4 phono-1/8 4 3 5 2 1 r20 100 c28 0.1uf x7r c29 0.1uf x7r c3 10uf elec + c5 0.1uf x7r u1 mc78m05acdt out 3 gnd 2 in 1 c4 0.1uf x7r c10 0.1uf c6 10uf elec c8 0.1uf x7r r2 4.7k r8 47 c27 1000pf npo r18 8.2k r13 10k c24 1000pf npo c19 10uf elec + j5 phono-1/8 4 3 5 2 1 j3 4x1hdr-au 1 2 3 4 r10 100k c13 10uf elec + r12 100k c16 10uf elec + r9 100k r14 6.8k c14 10uf elec + c26 0.1uf x7r j6 totx-173 1 2 3 4 5 6 c18 1uf elec c21 2.2uf z5u r21 1.5k 60 mil trace gnd_tie u2 CS4201 line_out_r 36 mono_out 37 avdd2 38 hp_out_l 39 gpio1/sdout 44 hp_out_r 41 avss2 42 gpio0/lrclk 43 hp_out_c 40 flto 34 flti 33 flt3d 32 hpcfg 31 dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 sync 10 dvdd2 9 reset# 11 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 24 avdd1 25 avss1 26 refflt 27 vrefout 28 aflt1 29 aflt2 30 spdo/sdo2 48 eapd/sclk 47 id1# 46 id0# 45 line_out_l 35 agnd agnd agnd agnd dgnd agnd agnd agnd dgnd agnd agnd dgnd +5va +12v agnd agnd dgnd +3.3vd dgnd dgnd +5vd agnd agnd agnd agnd +5va dgnd agnd async arst# abitclk asdout asdin pc speaker in cd in mic in aux in line in line out/ headphone jack s/pdif out ac link pci audio controller or ich controller mic in -3 db roll-off frequencies at 60 hz. and 16 khz in accordance with pc-99 (50 ppm) tie at one point only under the codec + figure 29. CS4201 reference design
CS4201 66 ds483pp3 15. references 1) cirrus logic, audio quality measurement specification , version 1.0, 1997 http://www.cirrus.com/products/papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998 3) cirrus logic, an22: overview of digital audio interface data structures , version 2.0, february 1998 4) cirrus logic, an134: aes and s/pdif recommended transformers , version 2, april 1999 5) cirrus logic, an165: cs4297a/cs4299 emi reduction techniques , version 1.0, september 1999 6) intel ? , audio codec ? 97 component specification , revision 2.1, may 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm 7) microsoft ? , pc 99 system design guide , version 1.0, july 1999 http://www.microsoft.com/hwdev/desguid/ 8) microsoft ? , pc 2001 system design guide , version 0.9, august 2000 http://www.pcdesguide.org/pc2001/default.htm 9) intel ? 82801aa (ich) and 82801ab (ich0) i/o controller hub , june 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm4
CS4201 ds483pp3 67 16. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a

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